Datasheet

Appendix A Electrical Characteristics
MC9S08JM60 Series Data Sheet, Rev. 3
Freescale Semiconductor 351
The average chip-junction temperature (T
J
) in °C can be obtained from:
T
J
= T
A
+ (P
D
× θ
JA
) Eqn. A-1
where:
T
A
= Ambient temperature, °C
θ
JA
= Package thermal resistance, junction-to-ambient, °C/W
P
D
= P
int
+ P
I/O
P
int
= I
DD
× V
DD
, Watts — chip internal power
P
I/O
= Power dissipation on input and output pins — user determined
For most applications, P
I/O
<< P
int
and can be neglected. An approximate relationship between P
D
and T
J
(if P
I/O
is neglected) is:
P
D
= K ÷ (T
J
+ 273°C) Eqn. A-2
Solving equations 1 and 2 for K gives:
K = P
D
× (T
A
+ 273°C) + θ
JA
× (P
D
)
2
Eqn. A-3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
P
D
(at equilibrium) for a known T
A
. Using this value of K, the values of P
D
and T
J
can be obtained by
solving equations 1 and 2 iteratively for any value of T
A
.
A.5 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions must be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM) and the Charge Device Model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.