Datasheet

Chapter 2 Pins and Connections
MC9S08JM60 Series Data Sheet, Rev. 3
Freescale Semiconductor 29
Figure 2-4. Basic System Connections
MC9S08JM60
V
DD
V
SS
RESET
OPTIONAL
MANUAL
RESET
PORT
A
V
DD
1
BACKGROUND HEADER
C
BY
0.1 μF
C
BLK
10 μF
+
5 V
+
SYSTEM
POWER
I/O AND
PERIPHERAL
INTERFACE TO
SYSTEM
APPLICATION
PTA0–PTA5
V
DD
PORT
B
PTB0/MISO2/ADP0
PTB1/MOSI2/ADP1
PTB2/SPSCK2/ADP2
PTB3/SS2
/ADP3
PTB4/KBIP4/ADP4
PTB5/KBIP5/ADP5
PTB6/ADP6
PTB7/ADP7
PORT
C
PTC0/SCL
PTC1/SDA
PTC2
PTC3/TxD2
PTC4
PTC5/RxD2
PTC6
PORT
D
PTD0/ADP8/ACMP+
PTD1/ADP9/ACMP–
PTD4/ADP11
PTD5
PTD6
PTD7
PTE0/TxD1
PTE1/RxD1
PTE2/TPM1CH0
PTE3/TPM1CH1
PTE4/MISO1
PTE5/MOSI1
PTE6/SPSCK1
PTE7/SS1
PTG0/KBIP0
PTG1/KBIP1
PTG2/KBIP6
PTG3/KBIP7
PTF0/TPM1CH2
PTF1/TPM1CH3
PTF2/TPM1CH4
PTF3/TPM1CH5
PTF4/TPM2CH0
PTF5/TPM2CH1
PTF6
PTF7
IRQ
ASYNCHRONOUS
INTERRUPT
INPUT
NOTES:
1. External crystal circuity is not required if using the MCG internal clock option. For USB operation, an external crystal is required.
2. XTAL and EXTAL are the same pins as PTG4 and PTG5, respectively.
3. RC filters on RESET
and IRQ are recommended for EMC-sensitive applications.
4. R
PUDP
is shown for full-speed USB only. The diagram shows a configuration where the on-chip regulator and R
PUDP
are enabled.
The voltage regulator output is used for R
PUDP.
R
PUDP
can optionally be disabled if using an external pullup resistor on USBDP
5. V
BUS
is a 5.0-V supply from upstream port that can be used for USB operation
6. USBDP and USBDN are powered by the 3.3-V regulator or external 3.3-V supply on V
USB33
.
V
DDAD
V
SSAD
C
BYAD
0.1 μF
V
REFL
V
REFH
PTG4/XTAL
PTG5/EXTAL
V
DD
4.7 k Ω –
0.1
μ F
V
DD
4.7 k Ω –10 k Ω
0.1 μ F
10 k
Ω
2
43
USBDN
V
USB33
USBDP
V
Bus
PORT
E
PORT
F
PORT
G
USB SERIES-B CONNECTOR
V
USB33
3.3-V Reference
R
PUDP
PTD2/KBIP2/ACMPO
PTD3/KBIP3/ADP10
BKGD/MS
XTAL
EXTAL
C2
C1
X1
R
F
R
S
NOTE 1
V
SSOSC
0.47 μ F
+
4.7
μ F