Datasheet

Serial Peripheral Interface (S08SPI16V1)
MC9S08JM60 Series Data Sheet, Rev. 3
252 Freescale Semiconductor
15.3.3 SPI Baud Rate Register (SPIxBR)
This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
Table 15-4. Bidirectional Pin Configurations
Pin Mode SPC0 BIDIROE MISO MOSI
Master Mode of Operation
Normal 0 X Master In Master Out
Bidirectional 1 0 MISO not used by SPI Master In
1 Master I/O
Slave Mode of Operation
Normal 0 X Slave Out Slave In
Bidirectional 1 0 Slave In MOSI not used by SPI
1Slave I/O
76543210
R0
SPPR2 SPPR1 SPPR0
0
SPR2 SPR1 SPR0
W
Reset00000000
= Unimplemented or Reserved
Figure 15-7. SPI Baud Rate Register (SPIxBR)
Table 15-5. SPIxBR Register Field Descriptions
Field Description
6:4
SPPR[2:0]
SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler
as shown in Ta bl e 1 5- 6. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler
drives the input of the SPI baud rate divider (see Figure 15-15). See Section 15.4.6, “SPI Baud Rate Generation,”
for details.
2:0
SPR[2:0]
SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in
Ta bl e 1 5- 7. The input to this divider comes from the SPI baud rate prescaler (see Figure 15-15). See
Section 15.4.6, “SPI Baud Rate Generation,” for details.