Datasheet

Serial Peripheral Interface (S08SPI16V1)
MC9S08JM60 Series Data Sheet, Rev. 3
248 Freescale Semiconductor
Figure 15-4. SPI Module Block Diagram
15.2 External Signal Description
The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control
bits. When the SPI is disabled (SPE = 0), these four pins revert to being general-purpose port I/O pins that
are not controlled by the SPI.
15.2.1 SPSCK — SPI Serial Clock
When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master,
this pin is the serial clock output.
SPIE
SPI SHIFT REGISTER
SHIFT
CLOCK
SHIFT
DIRECTION
Rx BUFFER
FULL
Tx BUFFER
EMPTY
SHIFT
OUT
SHIFT
IN
ENABLE
SPI SYSTEM
CLOCK
LOGIC
CLOCK GENERATOR
BUS RATE
CLOCK
MASTER/SLAVE
MODE SELECT
MODE FAULT
DETECTION
MASTER CLOCK
SLAVE CLOCK
SPI
INTERRUPT
REQUEST
PIN CONTROL
M
S
MASTER/
SLAVE
MOSI
(MOMI)
MISO
(SISO)
SPSCK
SS
M
S
S
M
MODF
SPE
LSBFE
MSTR
SPRF
SPTEF
SPTIE
MODFEN
SSOE
SPC0
BIDIROE
SPIBR
Tx BUFFER (WRITE SPIxDH:SPIxDL)
Rx BUFFER (READ SPIxDH:SPIxDL)
8 OR 16
BIT MODE
SPIMODE
16-BIT COMPARATOR
SPMF
SPMIE
SPIxMH:SPIxML
16-BIT LATCH