Datasheet
Chapter 1 Device Overview
MC9S08JM60 Series Data Sheet, Rev. 3
22 Freescale Semiconductor
Figure 1-2. System Clock Distribution Diagram
The MCG supplies the following clock sources:
• MCGOUT — This clock source is used as the CPU, USB RAM and USB module clock, and is
divided by two to generate the peripheral bus clock (BUSCLK). Control bits in the MCG control
registers determine which of the three clock sources is connected:
— Internal reference clock
— External reference clock
— Frequency-locked loop (FLL) or Phase-locked loop (PLL) output
See Chapter 12, “Multi-Purpose Clock Generator (S08MCGV1),” for details on configuring the
MCGOUT clock.
• MCGLCLK — This clock source is derived from the digitally controlled oscillator (DCO) of the
MCG. Development tools can select this internal self-clocked source to speed up BDC
communications in systems where the bus clock is slow.
• MCGIRCLK — This is the internal reference clock and can be selected as the real-time counter
clock source. Chapter 12, “Multi-Purpose Clock Generator (S08MCGV1),” explains the
MCGIRCLK in more detail. See Chapter 13, “Real-Time Counter (S08RTCV1),” for more
information regarding the use of MCGIRCLK.
• MCGERCLK — This is the external reference clock and can be selected as the clock source of
real-time counter and ADC module. Section 12.4.6, “External Reference Clock,” explains the
MCGERCLK in more detail. See Chapter 13, “Real-Time Counter (S08RTCV1),” and Chapter 10,
TPM1 TPM2 IIC SCI1 SCI2
BDC
CPU
ADC
2
RAM Flash
3
MCG
MCGOUT
÷2
BUSCLK
MCGLCLK
MCGERCLK
COP
1. The FFCLK is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency.
3. Flash has the frequency requirements for program and erase operation. See the Appendix A, “Electrical Characteristics,” for
details.
2. ADC has min. and max. frequency requirements. See Chapter 10, “Analog-to-Digital Converter (S08ADC12V1),”
and Appendix A, “Electrical Characteristics,” for det ail s.
XOSC
EXTAL XTAL
SPI1
FFCLK
1
MCGFFCLK
RTC
1 kHz
LPO
TPMCLK
MCGIRCLK
÷2
SPI2
USB
USB RAM
LPO clock