Datasheet

Multi-Purpose Clock Generator (S08MCGV1)
MC9S08JM60 Series Data Sheet, Rev. 3
Freescale Semiconductor 205
12.5.2.3 Example #3: Moving from BLPI to FEE Mode: External Crystal = 4 MHz,
Bus Frequency = 16 MHz
In this example, the MCG will move through the proper operational modes from BLPI mode at a 16 kHz
bus frequency running off of the internal reference clock (see previous example) to FEE mode using a 4
MHz crystal configured for a 16 MHz bus frequency. First, the code sequence will be described. Then a
flowchart will be included which illustrates the sequence.
1. First, BLPI must transition to FBI mode.
a) MCGC2 = 0x00 (%00000000)
– LP (bit 3) in MCGSC is 0
b) Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has acquired
lock. Although the FLL is bypassed in FBI mode, it is still enabled and running.
2. Next, FBI will transition to FEE mode.
a) MCGC2 = 0x36 (%00110110)
– RANGE (bit 5) set to 1 because the frequency of 4 MHz is within the high frequency range
– HGO (bit 4) set to 1 to configure external oscillator for high gain operation
– EREFS (bit 2) set to 1, because a crystal is being used
– ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active
b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit
has been initialized.
c) MCGC1 = 0x38 (%00111000)
– CLKS (bits 7 and 6) set to %00 in order to select the output of the FLL as system clock
source
– RDIV (bits 5-3) set to %111, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is
in the 31.25 kHz to 39.0625 kHz range required by the FLL
– IREFS (bit 1) cleared to 0, selecting the external reference clock
d) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference clock is the current
source for the reference clock
e) Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has
reacquired lock.
f) Loop until CLKST (bits 3 and 2) in MCGSC are %00, indicating that the output of the FLL is
selected to feed MCGOUT