Datasheet

MC9S08JM60 Series Data Sheet, Rev. 3
178 Freescale Semiconductor
Figure 11-12. Typical IIC Interrupt Routine
Clear
Master
Mode
?
Tx/Rx
?
Last Byte
Transmitted
?
RXAK=0
?
End of
Addr Cycle
(Master Rx)
?
Write Next
Byte to IICD
Switch to
Rx Mode
Dummy Read
from IICD
Generate
Stop Signal
Read Data
from IICD
and Store
Set TXACK =1
Generate
Stop Signal
2nd Last
Byte to Be Read
?
Last
Byte to Be Read
?
Arbitration
Lost
?
Clear ARBL
IAAS=1
?
IAAS=1
?
SRW=1
?
TX/RX
?
Set TX
Mode
Write Data
to IICD
Set RX
Mode
Dummy Read
from IICD
ACK from
Receiver
?
Tx Next
Byte
Read Data
from IICD
and Store
Switch to
Rx Mode
Dummy Read
from IICD
RTI
YN
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
Y
TX RX
RX
TX
(Write)
(Read)
N
IICIF
Address Transfer
Data Transfer
(MST = 0)
(MST = 0)
See Note 1
NOTES:
1. If general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). If the received address was a
general call address, then the general call must be handled by user software.
2. When 10-bit addressing is used to address a slave, the slave sees an interrupt following the first byte of the extended address.
See Note 2