Datasheet

Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08JM60 Series Data Sheet, Rev. 3
Freescale Semiconductor 117
Table 7-3. Opcode Map (Sheet 1 of 2)
Bit-Manipulation Branch Read-Modify-Write Control Register/Memory
00 5
BRSET0
3DIR
10 5
BSET0
2DIR
20 3
BRA
2REL
30 5
NEG
2DIR
40 1
NEGA
1INH
50 1
NEGX
1INH
60 5
NEG
2IX1
70 4
NEG
1IX
80 9
RTI
1INH
90 3
BGE
2REL
A0 2
SUB
2IMM
B0 3
SUB
2DIR
C0 4
SUB
3 EXT
D0 4
SUB
3IX2
E0 3
SUB
2IX1
F0 3
SUB
1IX
01 5
BRCLR0
3DIR
11 5
BCLR0
2DIR
21 3
BRN
2REL
31 5
CBEQ
3DIR
41 4
CBEQA
3IMM
51 4
CBEQX
3IMM
61 5
CBEQ
3IX1+
71 5
CBEQ
2IX+
81 6
RTS
1INH
91 3
BLT
2REL
A1 2
CMP
2IMM
B1 3
CMP
2DIR
C1 4
CMP
3 EXT
D1 4
CMP
3IX2
E1 3
CMP
2IX1
F1 3
CMP
1IX
02 5
BRSET1
3DIR
12 5
BSET1
2DIR
22 3
BHI
2REL
32 5
LDHX
3EXT
42 5
MUL
1INH
52 6
DIV
1INH
62 1
NSA
1INH
72 1
DAA
1INH
82 5+
BGND
1INH
92 3
BGT
2REL
A2 2
SBC
2IMM
B2 3
SBC
2DIR
C2 4
SBC
3 EXT
D2 4
SBC
3IX2
E2 3
SBC
2IX1
F2 3
SBC
1IX
03 5
BRCLR1
3DIR
13 5
BCLR1
2DIR
23 3
BLS
2REL
33 5
COM
2DIR
43 1
COMA
1INH
53 1
COMX
1INH
63 5
COM
2IX1
73 4
COM
1IX
83 11
SWI
1INH
93 3
BLE
2REL
A3 2
CPX
2IMM
B3 3
CPX
2DIR
C3 4
CPX
3 EXT
D3 4
CPX
3IX2
E3 3
CPX
2IX1
F3 3
CPX
1IX
04 5
BRSET2
3DIR
14 5
BSET2
2DIR
24 3
BCC
2REL
34 5
LSR
2DIR
44 1
LSRA
1INH
54 1
LSRX
1INH
64 5
LSR
2IX1
74 4
LSR
1IX
84 1
TA P
1INH
94 2
TXS
1INH
A4 2
AND
2IMM
B4 3
AND
2DIR
C4 4
AND
3 EXT
D4 4
AND
3IX2
E4 3
AND
2IX1
F4 3
AND
1IX
05 5
BRCLR2
3DIR
15 5
BCLR2
2DIR
25 3
BCS
2REL
35 4
STHX
2DIR
45 3
LDHX
3IMM
55 4
LDHX
2DIR
65 3
CPHX
3IMM
75 5
CPHX
2DIR
85 1
TPA
1INH
95 2
TSX
1INH
A5 2
BIT
2IMM
B5 3
BIT
2DIR
C5 4
BIT
3 EXT
D5 4
BIT
3IX2
E5 3
BIT
2IX1
F5 3
BIT
1IX
06 5
BRSET3
3DIR
16 5
BSET3
2DIR
26 3
BNE
2REL
36 5
ROR
2DIR
46 1
RORA
1INH
56 1
RORX
1INH
66 5
ROR
2IX1
76 4
ROR
1IX
86 3
PULA
1INH
96 5
STHX
3EXT
A6 2
LDA
2IMM
B6 3
LDA
2DIR
C6 4
LDA
3 EXT
D6 4
LDA
3IX2
E6 3
LDA
2IX1
F6 3
LDA
1IX
07 5
BRCLR3
3DIR
17 5
BCLR3
2DIR
27 3
BEQ
2REL
37 5
ASR
2DIR
47 1
ASRA
1INH
57 1
ASRX
1INH
67 5
ASR
2IX1
77 4
ASR
1IX
87 2
PSHA
1INH
97 1
TA X
1INH
A7 2
AIS
2IMM
B7 3
STA
2DIR
C7 4
STA
3 EXT
D7 4
STA
3IX2
E7 3
STA
2IX1
F7 2
STA
1IX
08 5
BRSET4
3DIR
18 5
BSET4
2DIR
28 3
BHCC
2REL
38 5
LSL
2DIR
48 1
LSLA
1INH
58 1
LSLX
1INH
68 5
LSL
2IX1
78 4
LSL
1IX
88 3
PULX
1INH
98 1
CLC
1INH
A8 2
EOR
2IMM
B8 3
EOR
2DIR
C8 4
EOR
3 EXT
D8 4
EOR
3IX2
E8 3
EOR
2IX1
F8 3
EOR
1IX
09 5
BRCLR4
3DIR
19 5
BCLR4
2DIR
29 3
BHCS
2REL
39 5
ROL
2DIR
49 1
ROLA
1INH
59 1
ROLX
1INH
69 5
ROL
2IX1
79 4
ROL
1IX
89 2
PSHX
1INH
99 1
SEC
1INH
A9 2
ADC
2IMM
B9 3
ADC
2DIR
C9 4
ADC
3 EXT
D9 4
ADC
3IX2
E9 3
ADC
2IX1
F9 3
ADC
1IX
0A 5
BRSET5
3DIR
1A 5
BSET5
2DIR
2A 3
BPL
2REL
3A 5
DEC
2DIR
4A 1
DECA
1INH
5A 1
DECX
1INH
6A 5
DEC
2IX1
7A 4
DEC
1IX
8A 3
PULH
1INH
9A 1
CLI
1INH
AA 2
ORA
2IMM
BA 3
ORA
2DIR
CA 4
ORA
3 EXT
DA 4
ORA
3IX2
EA 3
ORA
2IX1
FA 3
ORA
1IX
0B 5
BRCLR5
3DIR
1B 5
BCLR5
2DIR
2B 3
BMI
2REL
3B 7
DBNZ
3DIR
4B 4
DBNZA
2INH
5B 4
DBNZX
2INH
6B 7
DBNZ
3IX1
7B 6
DBNZ
2IX
8B 2
PSHH
1INH
9B 1
SEI
1INH
AB 2
ADD
2IMM
BB 3
ADD
2DIR
CB 4
ADD
3 EXT
DB 4
ADD
3IX2
EB 3
ADD
2IX1
FB 3
ADD
1IX
0C 5
BRSET6
3DIR
1C 5
BSET6
2DIR
2C 3
BMC
2REL
3C 5
INC
2DIR
4C 1
INCA
1INH
5C 1
INCX
1INH
6C 5
INC
2IX1
7C 4
INC
1IX
8C 1
CLRH
1INH
9C 1
RSP
1INH
BC 3
JMP
2DIR
CC 4
JMP
3 EXT
DC 4
JMP
3IX2
EC 3
JMP
2IX1
FC 3
JMP
1IX
0D 5
BRCLR6
3DIR
1D 5
BCLR6
2DIR
2D 3
BMS
2REL
3D 4
TST
2DIR
4D 1
TSTA
1INH
5D 1
TSTX
1INH
6D 4
TST
2IX1
7D 3
TST
1IX
9D 1
NOP
1INH
AD 5
BSR
2REL
BD 5
JSR
2DIR
CD 6
JSR
3 EXT
DD 6
JSR
3IX2
ED 5
JSR
2IX1
FD 5
JSR
1IX
0E 5
BRSET7
3DIR
1E 5
BSET7
2DIR
2E 3
BIL
2REL
3E 6
CPHX
3EXT
4E 5
MOV
3DD
5E 5
MOV
2DIX+
6E 4
MOV
3IMD
7E 5
MOV
2IX+D
8E 2+
STOP
1INH
9E
Page 2
AE 2
LDX
2IMM
BE 3
LDX
2DIR
CE 4
LDX
3 EXT
DE 4
LDX
3IX2
EE 3
LDX
2IX1
FE 3
LDX
1IX
0F 5
BRCLR7
3DIR
1F 5
BCLR7
2DIR
2F 3
BIH
2REL
3F 5
CLR
2DIR
4F 1
CLRA
1INH
5F 1
CLRX
1INH
6F 5
CLR
2IX1
7F 4
CLR
1IX
8F 2+
WAIT
1INH
9F 1
TXA
1INH
AF 2
AIX
2IMM
BF 3
STX
2DIR
CF 4
STX
3 EXT
DF 4
STX
3IX2
EF 3
STX
2IX1
FF 2
STX
1IX
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset
IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment
DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with
IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment
Opcode in
Hexadecimal
Number of Bytes
F0 3
SUB
1IX
HCS08 Cycles
Instruction Mnemonic
Addressing Mode