Datasheet

Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08JM60 Series Data Sheet, Rev. 3
Freescale Semiconductor 113
MOV opr8a,opr8a
MOV opr8a,X+
MOV #opr8i,opr8a
MOV ,X+,opr8a
Move
(M)
destination
← (M)
source
In IX+/DIR and DIR/IX+ Modes,
H:X ← (H:X) + $0001
DIR/DIR
DIR/IX+
IMM/DIR
IX+/DIR
4E
5E
6E
7E
dd dd
dd
ii dd
dd
5
5
4
5
rpwpp
rfwpp
pwpp
rfwpp
0 – –   –
MUL
Unsigned multiply
X:A ← (X) × (A)
INH 42 5 ffffp – 0– – – 0
NEG opr8a
NEGA
NEGX
NEG oprx8,X
NEG ,X
NEG oprx8,SP
Negate M ← – (M) = $00 – (M)
(Two’s Complement) A ← – (A) = $00 – (A)
X ← – (X) = $00 – (X)
M ← – (M) = $00 – (M)
M ← – (M) = $00 – (M)
M ← – (M) = $00 – (M)
DIR
INH
INH
IX1
IX
SP1
30
40
50
60
70
9E 60
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
 ––   
NOP No Operation — Uses 1 Bus Cycle INH 9D 1 p – – – – – –
NSA
Nibble Swap Accumulator
A ← (A[3:0]:A[7:4])
INH 62 1 p – – – – – –
ORA #opr8i
ORA opr8a
ORA opr16a
ORA oprx16,X
ORA oprx8,X
ORA ,X
ORA oprx16,SP
ORA oprx8,SP
Inclusive OR Accumulator and Memory
A ← (A) | (M)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AA
BA
CA
DA
EA
FA
9E DA
9E EA
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
0 – –   –
PSHA
Push Accumulator onto Stack
Push (A); SP ← (SP) – $0001
INH 87 2 sp – – – – – –
PSHH
Push H (Index Register High) onto Stack
Push (H); SP ← (SP) – $0001
INH 8B 2 sp – – – – – –
PSHX
Push X (Index Register Low) onto Stack
Push (X); SP ← (SP) – $0001
INH 89 2 sp – – – – – –
PULA
Pull Accumulator from Stack
SP ← (SP + $0001); Pull (A)
INH 86 3 ufp – – – – – –
PULH
Pull H (Index Register High) from Stack
SP ← (SP + $0001); Pull (H)
INH 8A 3 ufp – – – – – –
PULX
Pull X (Index Register Low) from Stack
SP ← (SP + $0001); Pull (X)
INH 88 3 ufp – – – – – –
ROL opr8a
ROLA
ROLX
ROL oprx8,X
ROL ,X
ROL oprx8,SP
Rotate Left through Carry
DIR
INH
INH
IX1
IX
SP1
39
49
59
69
79
9E 69
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
 ––   
ROR opr8a
RORA
RORX
ROR oprx8,X
ROR ,X
ROR oprx8,SP
Rotate Right through Carry
DIR
INH
INH
IX1
IX
SP1
36
46
56
66
76
9E 66
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
 ––   
Table 7-2. . Instruction Set Summary (Sheet 6 of 9)
Source
Form
Operation
Address
Mode
Object Code
Cycles
Cyc-by-Cyc
Details
Affect
on CCR
VH I N Z C
C
b0
b7
b0
b7
C