MC9S08JM60 MC9S08JM32 Data Sheet HCS08 Microcontrollers MC9S08JM60 Rev. 3 1/2009 freescale.
MC9S08JM60 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • • • • • 48-MHz HCS08 CPU (central processor unit) 24-MHz internal bus frequency HC08 instruction set with added BGND instruction Background debugging system Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) • In-circuit emulator (ICE) debug module containing two comparators and nine trigger modes.
MC9S08JM60 Series Data Sheet Covers MC9S08JM60 MC9S08JM32 MC9S08JM60 Rev.
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List of Chapters Chapter Number Title Page Chapter 1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 2 Pins and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Chapter 3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Chapter 4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents Section Number Title Page Chapter 1 Device Overview 1.1 1.2 1.3 Introduction .....................................................................................................................................19 MCU Block Diagram ......................................................................................................................19 System Clock Distribution ..............................................................................................................
4.5 4.6 4.7 Flash ................................................................................................................................................51 4.5.1 Features .............................................................................................................................51 4.5.2 Program and Erase Times .................................................................................................52 4.5.3 Program and Erase Command Execution ..............................
6.3 6.4 6.5 Pin Control ......................................................................................................................................82 6.3.1 Internal Pullup Enable ......................................................................................................83 6.3.2 Output Slew Rate Control Enable .....................................................................................83 6.3.3 Output Drive Strength Select ......................................................
Chapter 8 5 V Analog Comparator (S08ACMPV2) 8.1 8.2 8.3 8.4 Introduction ...................................................................................................................................119 8.1.1 ACMP Configuration Information ..................................................................................119 8.1.2 ACMP/TPM Configuration Information ........................................................................119 8.1.3 Features ...............................................
10.3.2 Status and Control Register 2 (ADCSC2) ......................................................................143 10.3.3 Data Result High Register (ADCRH) .............................................................................143 10.3.4 Data Result Low Register (ADCRL) ..............................................................................144 10.3.5 Compare Value High Register (ADCCVH) ....................................................................144 10.3.
11.6 Interrupts .......................................................................................................................................175 11.6.1 Byte Transfer Interrupt ....................................................................................................175 11.6.2 Address Detect Interrupt .................................................................................................176 11.6.3 Arbitration Lost Interrupt .......................................................
Chapter 14 Serial Communications Interface (S08SCIV4) 14.1 Introduction ...................................................................................................................................223 14.1.1 Features ...........................................................................................................................225 14.1.2 Modes of Operation ........................................................................................................225 14.1.3 Block Diagram .......
15.4.5 SPI Clock Formats ..........................................................................................................259 15.4.6 SPI Baud Rate Generation ..............................................................................................261 15.4.7 Special Features ..............................................................................................................262 15.4.8 Error Conditions .....................................................................................
.2.3 VUSB33 ............................................................................................................................................................. 300 17.3 Register Definition ........................................................................................................................300 17.3.1 USB Control Register 0 (USBCTL0) .............................................................................301 17.3.2 Peripheral ID Register (PERID) ............................
Appendix A Electrical Characteristics A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 Introduction ....................................................................................................................................349 Parameter Classification.................................................................................................................349 Absolute Maximum Ratings...........................................................................................................
Chapter 1 Device Overview 1.1 Introduction MC9S08JM60 series MCUs are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. Table 1-1 summarizes the peripheral availability per package type for the devices available in the MC9S08JM60 series. Table 1-1.
Chapter 1 Device Overview USBDP USBDN HCS08 CORE PORT A ON-CHIP ICE AND DEBUG MODULE (DBG) USB SIE RESET IRQ/TPMCLK CPU HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT 8-/16-BIT SERIAL PERIPHERAL INTERFACE MODULE (SPI2) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) COP IRQ LVD IIC MODULE (IIC) VDDAD USER Flash (IN BYTES) MC9S08JM60 = 60,912 MC9S08JM32 = 32,768 SS2 SPSCK2 MOSI2 MISO2 RxD2 TxD2 SDA SCL 8 4 ACMP– ANALOG COMPARATOR (ACMP) ACMPO VDD VSS VUSB33
Chapter 1 Device Overview Table 1-2 lists the functional versions of the on-chip modules. Table 1-2. Versions of On-Chip Modules Module 1.
Chapter 1 Device Overview TPMCLK 1 kHz LPO LPO clock COP RTC TPM1 TPM2 IIC SCI1 SCI2 SPI1 SPI2 MCGERCLK MCGIRCLK MCG MCGFFCLK ÷2 MCGOUT ÷2 FFCLK1 BUSCLK MCGLCLK XOSC USB RAM EXTAL USB CPU BDC ADC2 RAM Flash3 XTAL 1. The FFCLK is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency. 2. ADC has min. and max. frequency requirements.
Chapter 1 Device Overview • • • “Analog-to-Digital Converter (S08ADC12V1),” for more information regarding the use of MCGERCLK with these modules. MCGFFCLK — This clock source is divided by 2 to generate FFCLK after being synchronized to the BUSCLK. It can be selected as clock source for the TPM modules. The frequency of the MCGFFCLK is determined by the settings of the MCG. See the Section 12.4.7, “Fixed Frequency Clock,” for details.
Chapter 1 Device Overview MC9S08JM60 Series Data Sheet, Rev.
Chapter 2 Pins and Connections 2.1 Introduction This chapter describes signals that connect to package pins. It includes pinout diagrams, a table of signal properties, and detailed discussion of signals. MC9S08JM60 Series Data Sheet, Rev.
Chapter 2 Pins and Connections PTC2 PTC1/SDA PTC0/SCL VSSOSC PTG5/EXTAL PTG4/XTAL BKGD/MS PTG3/KBIP7 PTG2/KBIP6 PTD7 PTD6 PTD5 PTD4/ADP11 63 62 61 60 59 58 57 56 55 54 53 52 51 50 64 PTC4 1 PTD3/KBIP3/ADP10 PTC3/TxD2 Device Pin Assignment PTC5/RxD2 49 48 PTD2/KBIP2/ACMPO IRQ/TPMCLK 2 47 VSSAD RESET 3 46 VREFL PTF0/TPM1CH2 4 45 VREFH PTF1/TPM1CH3 5 44 VDDAD PTF2/TPM1CH4 6 43 PTD1/ADP9/ACMP– PTF3/TPM1CH5 7 42 PTD0/ADP8/ACMP+ PTF4/TPM2CH0 8 41 PTB7/A
PTC2 PTC1/SDA PTC0/SCL VSSOSC PTG5/EXTAL PTG4/XTAL BKGD/MS PTG3/KBIP7 PTG2/KBIP6 47 46 45 44 43 42 41 40 39 38 37 48 PTC4 1 PTD7 PTC3/TxD2 PTC5/RxD2 Chapter 2 Pins and Connections 36 PTD2/KBIP2/ACMPO IRQ/TPMCLK 2 35 VSSAD/VREFL RESET 3 34 VDDAD/VREFH PTF0/TPM1CH2 4 33 PTD1/ADP9/ACMP– PTF1/TPM1CH3 5 32 PTD0/ADP8/ACMP+ PTF4/TPM2CH0 6 31 PTB5/KBIP5/ADP5 PTF5/TPM2CH1 7 30 PTB4/KBIP4/ADP4 PTF6 8 29 PTB3/SS2/ADP3 PTE0/TxD1 9 28 PTB2/SPSCK2/ADP2 PTE1/RxD1
PTG2/KBIP6 PTG3/KBIP7 BKGD/MS PTG4/XTAL PTG5/EXTAL VSSOSC PTC0/SCL PTC1/SDA PTC2 PTC3/TxD2 PTC5/RxD2 Chapter 2 Pins and Connections 34 44 43 PTC4 1 42 41 40 39 38 37 36 35 33 PTD2/KBIP2/ACMPO IRQ/TPMCLK 2 32 VSSAD/VREFL RESET 3 31 VDDAD/VREFH PTF0/TPM1CH2 4 30 PTD1/ADP9/ACMP– PTF1/TPM1CH3 5 29 PTD0/ADP8/ACMP+ 28 PTB5/KBIP5/ADP5 44-Pin LQFP PTF4/TPM2CH0 6 PTF5/TPM2CH1 7 27 PTB4/KBIP4/ADP4 PTE0/TxD1 8 26 PTB3/SS2/ADP3 PTE1/RxD1 9 25 PTB2/SPSCK2/ADP2 PTE
Chapter 2 Pins and Connections VREFH MC9S08JM60 VDDAD CBYAD 0.1 μF VSSAD VREFL VDD VDD SYSTEM POWER + CBLK + 10 μF 5V CBY 0.1 μF PORT B RF XTAL C1 C2 X1 VSSOSC RS PORT C EXTAL BACKGROUND HEADER VDD BKGD/MS VDD PORT D 4.7 kΩ–10 kΩ RESET 0.1 μF VDD OPTIONAL MANUAL RESET 4.7 kΩ– 10 kΩ ASYNCHRONOUS INTERRUPT INPUT IRQ 0.1 μF PORT E 3.3-V Reference + 4.7 μF 0.
Chapter 2 Pins and Connections 2.3.1 Power (VDD, VSS, VSSOSC, VDDAD, VSSAD, VUSB33) VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins.
Chapter 2 Pins and Connections 2.3.3 RESET Pin RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver, and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background debug connector, so a development system can directly reset the MCU system.
Chapter 2 Pins and Connections 2.3.7 USB Data Pins (USBDP, USBDN) The USBDP (D+) and USBDN (D–) pins are the analog input/output lines to/from full-speed internal USB transciever. An optional internal pullup resistor for the USBDP pin, RPUDP, is available. 2.3.8 General-Purpose I/O and Peripheral Ports The MC9S08JM60 series of MCUs support up to 51 general-purpose I/O pins, which are shared with on-chip peripheral functions (timers, serial I/O, ADC, keyboard interrupts, etc.).
Chapter 2 Pins and Connections Table 2-1.
Chapter 2 Pins and Connections NOTE When an alternative function is first enabled, it is possible to get a spurious edge to the module, user software must clear out any associated flags before interrupts are enabled. Table 2-1 illustrates the priority if multiple modules are enabled. The highest priority module will have control over the pin. Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module.
Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08JM60 series are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each mode are described. 3.2 • • • 3.
Chapter 3 Modes of Operation After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running.
Chapter 3 Modes of Operation 3.6 Stop Modes One of two stop modes is entered upon execution of a STOP instruction when STOPE in SOPT1 is set. In any stop mode, the bus and CPU clocks are halted. The MCG module can be configured to leave the reference clocks running. See Chapter 12, “Multi-Purpose Clock Generator (S08MCGV1),” for more information. Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various conditions.
Chapter 3 Modes of Operation 3.6.1.2 Active BDM Enabled in Stop Mode Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This register is described in Chapter 18, “Development Support.” If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode. Because of this, background debug communication remains possible.
Chapter 3 Modes of Operation writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. 3.6.3 On-Chip Peripheral Modules in Stop Modes When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.
Chapter 3 Modes of Operation MC9S08JM60 Series Data Sheet, Rev.
Chapter 4 Memory 4.1 MC9S08JM60 Series Memory Map Figure 4-1 shows the memory map for the MC9S08JM60 series. On-chip memory in the MC9S08JM60 series of MCUs consists of RAM, flash program memory for nonvolatile data storage, plus I/O and control/status registers. The registers are divided into three groups: • Direct-page registers (0x0000 through 0x00AF) • High-page registers (0x1800 through 0x185F) • Nonvolatile registers (0xFFB0 through 0xFFBF) MC9S08JM60 Series Data Sheet, Rev.
Chapter 4 Memory 0x0000 0x00AF 0x00B0 DIRECT PAGE REGISTERS 0x0000 0x00AF 0x00B0 DIRECT PAGE REGISTERS RAM 2048 BYTES RAM 4096 BYTES 0x10AF 0x10B0 0x17FF 0x1800 0x185F 0x1860 0x08AF 0x08B0 UNIMPLEMENTED FLASH 1872 BYTES HIGH PAGE REGISTERS 96 BYTES 3936 BYTES 0x17FF 0x1800 0x185F 0x1860 USB RAM — 256 BYTES 0x195F 0x1960 HIGH PAGE REGISTERS 96 BYTES USB RAM — 256 BYTES 0x195F 0x1960 UNIMPLEMENTED 0x7FFF 0x8000 FLASH 59,088 BYTES FLASH 32,768 BYTES 0xFFFF 0xFFFF MC9S08JM32 MC9S08JM60 Figure 4-
Chapter 4 Memory Table 4-1. Reset and Interrupt Vectors (continued) 4.
Chapter 4 Memory — An 8-byte backdoor comparison key which optionally allows a user to gain controlled access to secure memory Because the nonvolatile register locations are flash memory, they must be erased and programmed like other flash memory locations. Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation instructions can be used to access any bit in any direct-page register.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-3.
Chapter 4 Memory Table 4-3. High-Page Register Summary (Sheet 3 of 3) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x1857 Reserved — — — — — — — — 0x1858 PTGPE — — PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0 0x1859 PTGSE — — PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0 0x185A PTGDS — — PTGDS5 PTGDS4 PTGDS3 PTGDS2 PTGDS1 PTGDS0 0x185B– 0x185F Reserved — — — — — — — — 1 This reserved bit must always be written to 0.
Chapter 4 Memory The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention. For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF.
Chapter 4 Memory 4.5.2 Program and Erase Times Before any program or erase command can be accepted, the flash clock divider register (FCDIV) must be written to set the internal clock for the flash module to a frequency (fFCLK) between 150 kHz and 200 kHz (see Section 4.7.1, “Flash Clock Divider Register (FCDIV).”) This register can be written only once, so normally this write is done during reset initialization. FCDIV cannot be written if the access error flag, FACCERR in FSTAT, is set.
Chapter 4 Memory 2. Write the command code for the desired command to FCMD. The five valid commands are blank check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase (0x41). The command code is latched into the command buffer. 3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its address and data information).
Chapter 4 Memory 4.5.4 Burst Program Execution The burst program command is used to program sequential bytes of data in less time than would be required using the standard program command. This is possible because the high voltage to the flash array does not need to be disabled between program operations. Ordinarily, when a program or erase command is issued, an internal charge pump associated with the flash memory must be enabled to supply high voltage to the array.
Chapter 4 Memory Note 1: Required only once after reset. WRITE TO FCDIV (Note 1) FLASH BURST PROGRAM FLOW START FACCERR ? 1 0 CLEAR ERROR FCBEF ? 1 0 WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND (0x25) TO FCMD WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF (Note 2) FPVIO OR FACCERR ? NO YES Note 2: Wait at least four bus cycles before checking FCBEF or FCCF. YES ERROR EXIT NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE Figure 4-3. Flash Burst Program Flowchart 4.5.
Chapter 4 Memory • • • • • • • 4.5.6 Writing a second time to FCMD before launching the previous command (There is only one write to FCMD for every command.) Writing to any flash control register other than FCMD after writing to a flash address Writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41) to FCMD Writing any flash control register other than the write to FSTAT (to clear FCBEF and launch the command) after writing the command to FCMD.
Chapter 4 Memory bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and reprogram operation. 4.5.7 Vector Redirection Whenever any block protection is enabled, the reset and interrupt vectors will be protected. Vector redirection allows users to modify interrupt vector information without unprotecting bootloader and reset vector space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register located at address 0xFFBF to zero.
Chapter 4 Memory is no way to disengage security without completely erasing all flash locations. If KEYEN is 1, a secure user program can temporarily disengage security by: 1. Writing 1 to KEYACC in the FCNFG register. This makes the flash module interpret writes to the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be compared against the key rather than as the first step in a flash program or erase command. 2.
Chapter 4 Memory 4.7.1 Flash Clock Divider Register (FCDIV) Bit 7 of this register is a read-only status flag. Bits 6 through 0 may be read at any time but can be written only one time. Before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits.
Chapter 4 Memory Table 4-7. Flash Clock Divider Settings fBus PRDIV8 (Binary) DIV5:DIV0 (Decimal) fFCLK Program/Erase Timing Pulse (5 μs Min, 6.7 μs Max) 24 MHz 1 14 200 kHz 5 μs 20 MHz 1 12 192.3 kHz 5.2 μs 10 MHz 0 49 200 kHz 5 μs 8 MHz 0 39 200 kHz 5 μs 4 MHz 0 19 200 kHz 5 μs 2 MHz 0 9 200 kHz 5 μs 1 MHz 0 4 200 kHz 5 μs 200 kHz 0 0 200 kHz 5 μs 150 kHz 0 0 150 kHz 6.7 μs 4.7.
Chapter 4 Memory Table 4-9. Security States SEC01:SEC00 Description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure SEC01:SEC00 changes to 1:0 after successful backdoor key entry or a successful blank check of flash. 4.7.3 Flash Configuration Register (FCNFG) Bits 7 through 5 may be read or written at any time. Bits 4 through 0 always read 0 and cannot be written. R 7 6 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 KEYACC W Reset 0 0 0 = Unimplemented or Reserved Figure 4-7.
Chapter 4 Memory Table 4-11. FPROT Register Field Descriptions Field Description 7:1 FPS[7:1] Flash Protect Select Bits — When FPDIS = 0, this 7-bit field determines the ending address of unprotected flash locations at the high address end of the flash. Protected flash locations cannot be erased or programmed. 0 FPDIS 4.7.5 Flash Protection Disable 0 Flash block specified by FPS[7:1] is block protected (program and erase not allowed). 1 No flash block is protected.
Chapter 4 Memory Table 4-12. FSTAT Register Field Descriptions (continued) Field Description 4 FACCERR Access Error Flag — FACCERR is set automatically when the proper command sequence is not obeyed exactly (the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register has been initialized, or if the MCU enters stop while a command was in progress. For a more detailed discussion of the exact actions that are considered access errors, see Section 4.5.
Chapter 4 Memory It is not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism. MC9S08JM60 Series Data Sheet, Rev.
Chapter 5 Resets, Interrupts, and System Configuration 5.1 Introduction This chapter discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the MC9S08JM60 series. Some interrupt sources from peripheral modules are discussed in greater detail within other chapters of this data manual. This chapter gathers basic information about all reset and interrupt sources in one place for easy reference.
Chapter 5 Resets, Interrupts, and System Configuration Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status (SRS) register. 5.4 Computer Operating Properly (COP) Watchdog The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP counter periodically.
Chapter 5 Resets, Interrupts, and System Configuration 5.5 Interrupts Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine (ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events such as an edge on the IRQ pin or a timer-overflow event.
Chapter 5 Resets, Interrupts, and System Configuration 5.5.1 Interrupt Stack Frame Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer (SP) points at the next available byte location on the stack. The current values of CPU registers are stored on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR.
Chapter 5 Resets, Interrupts, and System Configuration The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), the device is a pullup or pull-down depending on the polarity chosen. If the user desires to use an external pullup or pull-down, the IRQPDD can be written to a 1 to turn off the internal device. BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to act as the IRQ input.
Chapter 5 Resets, Interrupts, and System Configuration Table 5-1.
Chapter 5 Resets, Interrupts, and System Configuration Table 5-1. Vector Summary (from Lowest to Highest Priority) (continued) Vector Number Address (High/Low) Vector Name Module Source Enable Description 1 0xFFFC:FFFD Vswi Core SWI Instruction — Software interrupt 0 0xFFFE:FFFF Vreset System control COP LVD RESET pin Illegal opcode LOC POR BDFR COPE LVDRE — ILOP CME POR BDFR Watchdog timer Low-voltage detect External pin Illegal opcode Loss of clock Power-on-reset BDM-forced reset 5.
Chapter 5 Resets, Interrupts, and System Configuration 5.7 Reset, Interrupt, and System Control Registers and Control Bits One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space are related to reset and interrupt systems. Refer to the direct-page register summary in Chapter 4, “Memory,” of this data sheet for the absolute address assignments for all registers. This section refers to registers and control bits only by their names.
Chapter 5 Resets, Interrupts, and System Configuration Table 5-2. IRQSC Register Field Descriptions (continued) Field Description 2 IRQACK IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF). Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1), IRQF cannot be cleared while the IRQ pin remains at its asserted level.
Chapter 5 Resets, Interrupts, and System Configuration Table 5-3. SRS Register Field Descriptions (continued) Field Description 5 COP Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out. This reset source may be blocked by COPE = 0. 0 Reset not caused by COP timeout. 1 Reset caused by COP timeout. 4 ILOP Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode.
Chapter 5 Resets, Interrupts, and System Configuration must be written during the user’s reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. 7 6 5 4 R COPT 3 2 0 0 0 0 1 0 1 1 STOPE W Reset 1 1 0 1 = Unimplemented or Reserved Figure 5-5. System Options Register (SOPT1) Table 5-5.
Chapter 5 Resets, Interrupts, and System Configuration 5.7.5 R System Options Register 2 (SOPT2) 7 6 COPCLKS1 COPW1 0 0 5 4 3 0 0 0 2 1 0 SPI1FE SPI2FE ACIC 1 1 0 W Reset 0 0 0 = Unimplemented or Reserved 1 This bit can be written only one time after reset. Additional writes are ignored. Figure 5-6. System Options Register 2 (SOPT2) Table 5-7.
Chapter 5 Resets, Interrupts, and System Configuration Table 5-8. SDIDH Register Field Descriptions Field 7:4 Reserved 3:0 ID[11:8] R Description Bits 7:4 are reserved. Reading these bits will result in an indeterminate value; writes have no effect. Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The MC9S08JM60 Series is hard coded to the value 0x016. See also ID bits in Table 5-9.
Chapter 5 Resets, Interrupts, and System Configuration Table 5-10. SPMSC1 Register Field Descriptions Field 7 LVWF 6 LVWACK Description Low-Voltage Warning Flag — The LVWF bit indicates the low-voltage warning status. 0 low-voltage warning is not present. 1 low-voltage warning is present or was present. Low-Voltage Warning Acknowledge — If LVWF = 1, a low-voltage condition has occurred.
Chapter 5 Resets, Interrupts, and System Configuration Table 5-11. SPMSC2 Register Field Descriptions Field Description 5 LVDV Low-Voltage Detect Voltage Select — This bit selects the low voltage detect (LVD) trip point setting.It also selects the warning voltage range. See Table 5-12. 4 LVWV Low-Voltage Warning Voltage Select — This bit selects the low voltage warning (LVW) trip point voltage. See Table 5-12.
Chapter 5 Resets, Interrupts, and System Configuration MC9S08JM60 Series Data Sheet, Rev.
Chapter 6 Parallel Input/Output 6.1 Introduction This chapter explains software controls related to parallel input/output (I/O). The MC9S08JM60 has seven I/O ports which include a total of 51 general-purpose I/O pins. See Chapter 2, “Pins and Connections,” for more information about the logic and hardware aspects of these pins. Not all pins are available on all devices. See Table 2-1 to determine which functions are available for a specific device.
Chapter 6 Parallel Input/Output PTxDDn D Output Enable Q PTxDn D Output Data Q 1 Port Read Data 0 Synchronizer Input Data BUSCLK Figure 6-1. Parallel I/O Block Diagram The data direction control bits determine whether the pin output driver is enabled, and they control what is read for port data register reads. Each port pin has a data direction register bit. When PTxDDn = 0, the corresponding pin is an input and reads of PTxD return the pin value.
Chapter 6 Parallel Input/Output 6.3.1 Internal Pullup Enable An internal pullup device can be enabled for each port pin by setting the corresponding bit in one of the pullup enable registers (PTxPEn). The pullup device is disabled if the pin is configured as an output by the parallel I/O control logic or any shared peripheral function regardless of the state of the corresponding pullup enable register bit. The pullup device is also disabled if the pin is controlled by an analog function. 6.3.
Chapter 6 Parallel Input/Output Refer to tables in Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O and pin control registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 6.5.1 Port A I/O Registers (PTAD and PTADD) Port A parallel I/O function is controlled by the registers listed below.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 0 0 0 0 0 0 R W Reset 0 0 Figure 6-4. Internal Pullup Enable for Port A (PTAPE) Table 6-3. PTADD Register Field Descriptions Field Description [5:0] Internal Pullup Enable for Port A Bits — Each of these control bits determines if the internal pullup device is PTAPE[5:0] enabled for the associated PTA pin.
Chapter 6 Parallel Input/Output 6.5.3 Port B I/O Registers (PTBD and PTBDD) Port B parallel I/O function is controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-7. Port B Data Register (PTBD) Table 6-6. PTBD Register Field Descriptions Field Description 7:0 PTBD[7:0] Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-9. Internal Pullup Enable for Port B (PTBPE) Table 6-8. PTBPE Register Field Descriptions Field Description 7:0 Internal Pullup Enable for Port B Bits — Each of these control bits determines if the internal pullup device is PTBPE[7:0] enabled for the associated PTB pin.
Chapter 6 Parallel Input/Output 6.5.5 Port C I/O Registers (PTCD and PTCDD) Port C parallel I/O function is controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0 0 0 0 0 0 0 0 R W Reset 0 Figure 6-12. Port C Data Register (PTCD) Table 6-11. PTCD Register Field Descriptions Field Description 6:0 PTCD[6:0] Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0 0 0 0 0 0 0 0 R W Reset 0 Figure 6-14. Internal Pullup Enable for Port C (PTCPE) Table 6-13. PTCPE Register Field Descriptions Field Description 6:0 Internal Pullup Enable for Port C Bits — Each of these control bits determines if the internal pullup device is PTCPE[6:0] enabled for the associated PTC pin.
Chapter 6 Parallel Input/Output 6.5.7 Port D I/O Registers (PTDD and PTDDD) Port D parallel I/O function is controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-17. Port D Data Register (PTDD) Table 6-16. PTDD Register Field Descriptions Field Description 7:0 PTDD[7:0] Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-19. Internal Pullup Enable for Port D (PTDPE) Table 6-18. PTDPE Register Field Descriptions Field Description 7:0 Internal Pullup Enable for Port D Bits — Each of these control bits determines if the internal pullup device is PTDPE[7:0] enabled for the associated PTD pin.
Chapter 6 Parallel Input/Output 6.5.9 Port E I/O Registers (PTED and PTEDD) Port E parallel I/O function is controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0 0 0 0 0 0 0 0 0 R W Reset Figure 6-22. Port E Data Register (PTED) Table 6-21. PTED Register Field Descriptions Field Description 7:0 PTED[7:0] Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-24. Internal Pullup Enable for Port E (PTEPE) Table 6-23. PTEPE Register Field Descriptions Field Description 7:0 Internal Pullup Enable for Port E Bits— Each of these control bits determines if the internal pullup device is PTEPE[7:0] enabled for the associated PTE pin.
Chapter 6 Parallel Input/Output 6.5.11 Port F I/O Registers (PTFD and PTFDD) Port F parallel I/O function is controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-27. Port F Data Register (PTFD) Table 6-26. PTFD Register Field Descriptions Field Description 7:0 PTFD[7:0] Port F Data Register Bits— For port F pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-29. Internal Pullup Enable for Port F (PTFPE) Table 6-28. PTFPE Register Field Descriptions Field Description 7:0 Internal Pullup Enable for Port F Bits — Each of these control bits determines if the internal pullup device is PTFPE[7:0] enabled for the associated PTF pin.
Chapter 6 Parallel Input/Output 6.5.13 Port G I/O Registers (PTGD and PTGDD) Port G parallel I/O function is controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0 0 0 0 0 0 0 R W Reset 0 0 Figure 6-32. Port G Data Register (PTGD) Table 6-31. PTGD Register Field Descriptions Field Description 5:0 PTGD[5:0] Port G Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0 0 0 0 0 0 0 R W Reset 0 0 Figure 6-34. Internal Pullup Enable for Port G Bits (PTGPE) Table 6-33. PTGPE Register Field Descriptions Field Description 5:0 PTGPEn Internal Pullup Enable for Port G Bits — Each of these control bits determines if the internal pullup device is enabled for the associated PTG pin.
Chapter 6 Parallel Input/Output MC9S08JM60 Series Data Sheet, Rev.
Chapter 7 Central Processor Unit (S08CPUV2) 7.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU.
Chapter 7 Central Processor Unit (S08CPUV2) 7.2 Programmer’s Model and CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) 8 15 INDEX REGISTER (LOW) 7 X 0 SP STACK POINTER 0 15 PROGRAM COUNTER 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C PC CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers 7.2.
Chapter 7 Central Processor Unit (S08CPUV2) 7.2.3 Stack Pointer (SP) This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can be any size up to the amount of available RAM. The stack is used to automatically save the return address for subroutine calls, the return address and CPU registers during interrupts, and for local variables.
Chapter 7 Central Processor Unit (S08CPUV2) 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Field Description 7 V Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
Chapter 7 Central Processor Unit (S08CPUV2) 7.3 Addressing Modes Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit binary address can uniquely identify any memory location. This arrangement means that the same instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile program space.
Chapter 7 Central Processor Unit (S08CPUV2) 7.3.5 Extended Addressing Mode (EXT) In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 7.3.6 Indexed Addressing Mode Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack pointer as the base reference. 7.3.6.
Chapter 7 Central Processor Unit (S08CPUV2) 7.3.6.7 SP-Relative, 16-Bit Offset (SP2) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4 Special Operations The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions.
Chapter 7 Central Processor Unit (S08CPUV2) interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain). For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H) is not saved on the stack as part of the interrupt sequence.
Chapter 7 Central Processor Unit (S08CPUV2) 7.4.5 BGND Instruction The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter the active background mode. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug interface.
Chapter 7 Central Processor Unit (S08CPUV2) 7.5 HCS08 Instruction Set Summary Table 7-2 provides a summary of the HCS08 instruction set in all possible addressing modes. The table shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for each addressing mode variation of each instruction.
Chapter 7 Central Processor Unit (S08CPUV2) Operation Object Code Cycles Source Form Address Mode Table 7-2. .
Chapter 7 Central Processor Unit (S08CPUV2) Operation BRA rel Branch Always (if I = 1) BRCLR n,opr8a,rel DIR (b0) DIR (b1) DIR (b2) DIR (b3) Branch if Bit n in Memory Clear (if (Mn) = 0) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 01 03 05 07 09 0B 0D 0F BRN rel Branch Never (if I = 0) REL 21 rr Branch if Bit n in Memory Set (if (Mn) = 1) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 00 02 04 06 08 0A 0C 0E dd dd dd dd dd dd dd dd BSET n,opr8a Set Bit n in Memory (Mn ← 1)
Chapter 7 Central Processor Unit (S08CPUV2) CMP CMP CMP CMP CMP CMP CMP CMP #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP Operation Compare Accumulator with Memory A–M (CCR Updated But Operands Not Changed) Object Code IMM DIR EXT IX2 IX1 IX SP2 SP1 A1 B1 C1 D1 E1 F1 9E D1 9E E1 ii dd hh ll ee ff ff ee ff ff Cycles Source Form Address Mode Table 7-2. .
Chapter 7 Central Processor Unit (S08CPUV2) INC opr8a INCA INCX INC oprx8,X INC ,X INC oprx8,SP Operation Increment M ← (M) + $01 A ← (A) + $01 X ← (X) + $01 M ← (M) + $01 M ← (M) + $01 M ← (M) + $01 Object Code Cycles Source Form Address Mode Table 7-2. .
Chapter 7 Central Processor Unit (S08CPUV2) Operation Object Code Affect on CCR VH I N Z C rpwpp rfwpp pwpp rfwpp 0– – 42 5 ffffp –0 – – – 0 DIR INH INH IX1 IX SP1 30 dd 40 50 60 ff 70 9E 60 ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp No Operation — Uses 1 Bus Cycle INH 9D 1 p –– – – – – Nibble Swap Accumulator A ← (A[3:0]:A[7:4]) INH 62 1 p –– – – – – Inclusive OR Accumulator and Memory A ← (A) | (M) IMM DIR EXT IX2 IX1 IX SP2 SP1 AA BA CA DA EA FA 9E DA 9E EA 2 3 4 4 3 3 5 4 p
Chapter 7 Central Processor Unit (S08CPUV2) Operation Object Code Cycles Source Form Address Mode Table 7-2. .
Chapter 7 Central Processor Unit (S08CPUV2) Operation Object Code VH I N Z C 83 11 sssssvvfppp INH 84 1 p Transfer Accumulator to X (Index Register Low) X ← (A) INH 97 1 p –– – – – – Transfer CCR to Accumulator A ← (CCR) INH 85 1 p –– – – – – DIR INH INH IX1 IX SP1 3D dd 4D 5D 6D ff 7D 9E 6D ff 4 1 1 4 3 5 rfpp p p rfpp rfp prfpp 0– SWI Software Interrupt PC ← (PC) + $0001 Push (PCL); SP ← (SP) – $0001 Push (PCH); SP ← (SP) – $0001 Push (X); SP ← (SP) – $0001 Push (A); SP ← (SP)
Chapter 7 Central Processor Unit (S08CPUV2) Operation Object Code Cycles Source Form Address Mode Table 7-2. . Instruction Set Summary (Sheet 9 of 9) Cyc-by-Cyc Details Affect on CCR VH I N Z C TXS Transfer Index Reg. to SP SP ← (H:X) – $0001 INH 94 2 fp –– – – – – WAIT Enable Interrupts; Wait for Interrupt I bit ← 0; Halt CPU INH 8F 2+ fp...
Chapter 7 Central Processor Unit (S08CPUV2) Table 7-3.
Chapter 7 Central Processor Unit (S08CPUV2) Table 7-3.
Chapter 8 5 V Analog Comparator (S08ACMPV2) 8.1 Introduction The analog comparator module (ACMP) provides a circuit for comparing two analog input voltages or for comparing one analog input voltage to an internal reference voltage. The comparator circuit is designed to operate across the full range of the supply voltage (rail to rail operation). NOTE MC9S08JM60 series devices operate at a higher voltage range (2.7 V to 5.5 V) and do not include stop1 mode. Therefore, please disregard references to stop1.
Chapter 8 5 V Analog Comparator (S08ACMPV2) USBDP USBDN PORT A ON-CHIP ICE AND DEBUG MODULE (DBG) HCS08 CORE USB SIE RESET IRQ/TPMCLK CPU HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP IRQ FULL SPEED USB USB ENDPOINT TRANSCEIVER RAM 8-/16-BIT SERIAL PERIPHERAL INTERFACE MODULE (SPI2) SERIAL COMMUNICATIONS VDDAD IIC MODULE (IIC) SDA SCL 8 4 ACMP– ANALOG COMPARATOR (ACMP) ACMPO VDD VSS VUSB33 LOW-POWER OSCILLATOR SYSTEM VOLTAGE REGULATOR SERIAL COMMUNIC
Analog Comparator (S08ACMPV2) 8.1.3 Features The ACMP has the following features: • Full rail to rail supply operation. • Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output. • Option to compare to fixed internal bandgap reference voltage. • Option to allow comparator output to be visible on a pin, ACMPO. • Can operate in stop3 mode 8.1.4 Modes of Operation This section defines the ACMP operation in wait, stop and background debug modes. 8.1.4.
Analog Comparator (S08ACMPV2) Internal Bus Internal Reference ACIE ACBGS ACME ACMP INTERRUPT REQUEST Status & Control Register ACF ACMP+ + Interrupt Control - ACMP- set ACF ACMOD ACOPE Comparator ACMPO Figure 8-2. Analog Comparator 5V (ACMP5) Block Diagram MC9S08JM60 Series Data Sheet, Rev.
Analog Comparator (S08ACMPV2) 8.2 External Signal Description The ACMP has two analog input pins, ACMP+ and ACMP- and one digital output pin ACMPO. Each of these pins can accept an input voltage that varies across the full operating voltage range of the MCU. As shown in Figure 8-2, the ACMP- pin is connected to the inverting input of the comparator, and the ACMP+ pin is connected to the comparator non-inverting input if ACBGS is a 0.
Analog Comparator (S08ACMPV2) 8.3.1.1 ACMP Status and Control Register (ACMPSC) ACMPSC contains the status flag and control bits which are used to enable and configure the ACMP. 7 6 5 4 3 ACME ACBGS ACF ACIE 0 0 0 0 R 2 1 0 ACO ACOPE ACMOD W Reset: 0 0 0 0 = Unimplemented Figure 8-3. ACMP Status and Control Register Table 8-2. ACMP Status and Control Register Field Descriptions Field 7 ACME Description Analog Comparator Module Enable — ACME enables the ACMP module.
Analog Comparator (S08ACMPV2) 8.4 Functional Description The analog comparator can be used to compare two analog input voltages applied to ACMP+ and ACMP-; or it can be used to compare an analog input voltage applied to ACMP- with an internal bandgap reference voltage. ACBGS is used to select between the bandgap reference voltage or the ACMP+ pin as the input to the non-inverting input of the analog comparator.
Analog Comparator (S08ACMPV2) MC9S08JM60 Series Data Sheet, Rev.
Chapter 9 Keyboard Interrupt (S08KBIV2) 9.1 Introduction The MC9S08JM60 series have one KBI module with eight keyboard interrupt inputs. See Chapter 2, “Pins and Connections,” for more information about the logic and hardware aspects of these pins. NOTE MC9S08JM60 series devices operate at a higher voltage range (2.7 V to 5.5 V) and do not include stop1 mode. Therefore, please disregard references to stop1. MC9S08JM60 Series Data Sheet, Rev.
Keyboard Interrupt (KBI) ModuleChapter 9 Keyboard Interrupt (S08KBIV2) USBDP USBDN HCS08 CORE PORT A ON-CHIP ICE AND DEBUG MODULE (DBG) USB SIE RESET IRQ/TPMCLK CPU HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT 8-/16-BIT SERIAL PERIPHERAL INTERFACE MODULE (SPI2) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) COP IRQ LVD IIC MODULE (IIC) VDDAD USER Flash (IN BYTES) MC9S08JM60 = 60,912 MC9S08JM32 = 32,768 SS2 SPSCK2 MOSI2 MISO2 RxD2 TxD2 SDA SCL 8 4 ACMP– ANALO
Keyboard Interrupts (S08KBIV2) 9.1.1 Features The KBI features include: • Up to eight keyboard interrupt pins with individual pin enable bits. • Each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling edge and low level (or both rising edge and high level) interrupt sensitivity. • One software enabled keyboard interrupt. • Exit from low-power modes. 9.1.2 Modes of Operation This section defines the KBI operation in wait, stop, and background debug modes. 9.
Keyboard Interrupts (S08KBIV2) BUSCLK KBACK VDD 1 KBIP0 0 S RESET KBF D CLR Q KBIPE0 SYNCHRONIZER CK KBEDG0 KEYBOARD INTERRUPT FF 1 KBIPn 0 S STOP STOP BYPASS KBI INTERRUPT REQUEST KBMOD KBIPEn KBIE KBEDGn Figure 9-2. KBI Block Diagram 9.2 External Signal Description The KBI input pins can be used to detect either falling edges, or both falling edge and low level interrupt requests.
Keyboard Interrupts (S08KBIV2) R 7 6 5 4 3 2 0 0 0 0 KBF 0 W Reset: 1 0 KBIE KBMOD 0 0 KBACK 0 0 0 0 0 0 = Unimplemented Figure 9-3. KBI Status and Control Register Table 9-2. KBISC Register Field Descriptions Field Description 7:4 Unused register bits, always read 0. 3 KBF Keyboard Interrupt Flag — KBF indicates when a keyboard interrupt is detected. Writes have no effect on KBF. 0 No keyboard interrupt detected. 1 Keyboard interrupt detected.
Keyboard Interrupts (S08KBIV2) 7 6 5 4 3 2 1 0 KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0 0 0 0 0 0 0 0 0 R W Reset: Figure 9-5. KBI Edge Select Register Table 9-4. KBIES Register Field Descriptions Field 7:0 KBEDGn 9.4 Description Keyboard Edge Selects — Each of the KBEDGn bits selects the falling edge/low level or rising edge/high level function of the corresponding pin). 0 Falling edge/low level. 1 Rising edge/high level.
Keyboard Interrupts (S08KBIV2) KBISC provided all enabled keyboard inputs are at their deasserted levels. KBF will remain set if any enabled KBI pin is asserted while attempting to clear by writing a 1 to KBACK. 9.4.3 KBI Pullup/Pulldown Resistors The KBI pins can be configured to use an internal pullup/pulldown resistor using the associated I/O port pullup enable register.
Keyboard Interrupts (S08KBIV2) MC9S08JM60 Series Data Sheet, Rev.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.1 Overview The 12-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. NOTE MC9S08JM60 series devices operate at a higher voltage range (2.7 V to 5.5 V) and do not include stop1 mode. Therefore, please disregard references to stop1. 10.1.1 Module Configurations This section provides information for configuring the ADC on this device. 10.1.1.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) Table 10-1.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) ADCSC2[ADTRG] bit. When enabled, the ADC will be triggered every time RTCINT matches RTCMOD. The RTC interrupt does not have to be enabled to trigger the ADC. The RTC can be configured to cause a hardware trigger in MCU run, wait, and stop3. 10.1.1.4 Analog Pin Enables The ADC on MC9S08JM60 series contains only two analog pin enable registers, APCTL1 and APCTL2. 10.1.1.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) USBDP USBDN PORT A ON-CHIP ICE AND DEBUG MODULE (DBG) HCS08 CORE USB SIE RESET IRQ/TPMCLK CPU HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP IRQ FULL SPEED USB USB ENDPOINT TRANSCEIVER RAM 8-/16-BIT SERIAL PERIPHERAL INTERFACE MODULE (SPI2) SERIAL COMMUNICATIONS VDDAD IIC MODULE (IIC) SDA SCL 8 4 ACMP– ANALOG COMPARATOR (ACMP) ACMPO VDD VSS VUSB33 LOW-POWER OSCILLATOR SYSTEM VOLTAGE REGULATOR SERIAL
Analog-to-Digital Converter (S08ADC12V1) 10.1.
Analog-to-Digital Converter (S08ADC12V1) ADIV ADLPC MODE ADLSMP ADTRG 2 ADCO ADCH 1 ADCCFG complete COCO ADCSC1 ADICLK Compare true AIEN 3 Async Clock Gen ADACK MCU STOP ADCK ÷2 ALTCLK abort transfer sample initialize ••• AD0 convert Control Sequencer ADHWT Bus Clock Clock Divide AIEN 1 COCO 2 ADVIN Interrupt SAR Converter AD27 VREFH Data Registers Sum VREFL Compare true 3 Compare Value Registers ACFGT Value Compare Logic ADCSC2 Figure 10-2.
Analog-to-Digital Converter (S08ADC12V1) 10.2.1 Analog Power (VDDAD) The ADC analog portion uses VDDAD as its power connection. In some packages, VDDAD is connected internally to VDD. If externally available, connect the VDDAD pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAD for good results. 10.2.2 Analog Ground (VSSAD) The ADC analog portion uses VSSAD as its ground connection. In some packages, VSSAD is connected internally to VSS.
Analog-to-Digital Converter (S08ADC12V1) 7 R 6 5 AIEN ADCO 0 0 4 3 2 1 0 1 1 COCO ADCH W Reset: 0 1 1 1 Figure 10-3. Status and Control Register (ADCSC1) Table 10-3. ADCSC1 Field Descriptions Field Description 7 COCO Conversion Complete Flag. The COCO flag is a read-only bit set each time a conversion is completed when the compare function is disabled (ACFE = 0).
Analog-to-Digital Converter (S08ADC12V1) 10.3.2 Status and Control Register 2 (ADCSC2) The ADCSC2 register controls the compare function, conversion trigger, and conversion active of the ADC module. 7 R 6 5 4 ADTRG ACFE ACFGT 0 0 0 ADACT 3 2 0 0 0 0 1 0 R1 R1 0 0 W Reset: 1 0 Bits 1 and 0 are reserved bits that must always be written to 0. Figure 10-4. Status and Control Register 2 (ADCSC2) Table 10-5.
Analog-to-Digital Converter (S08ADC12V1) If the MODE bits are changed, any data in ADCRH becomes invalid. R 7 6 5 4 3 2 1 0 0 0 0 0 ADR11 ADR10 ADR9 ADR8 0 0 0 0 0 0 0 0 W Reset: Figure 10-5. Data Result High Register (ADCRH) 10.3.4 Data Result Low Register (ADCRL) ADCRL contains the lower eight bits of the result of a 12-bit or 10-bit conversion, and all eight bits of an 8-bit conversion.
Analog-to-Digital Converter (S08ADC12V1) In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV[9:8]). These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the compare function is enabled. In 8-bit mode, ADCCVH is not used during compare. 10.3.6 Compare Value Low Register (ADCCVL) This register holds the lower 8 bits of the 12-bit or 10-bit compare value or all 8 bits of the 8-bit compare value.
Analog-to-Digital Converter (S08ADC12V1) Table 10-6. ADCCFG Register Field Descriptions (continued) Field Description 3:2 MODE Conversion Mode Selection. MODE bits are used to select between 12-, 10-, or 8-bit operation. See Table 10-8. 1:0 ADICLK Input Clock Select. ADICLK bits select the input clock source to generate the internal clock ADCK. See Table 10-9. Table 10-7.
Analog-to-Digital Converter (S08ADC12V1) Table 10-10. APCTL1 Register Field Descriptions Field Description 7 ADPC7 ADC Pin Control 7. ADPC7 controls the pin associated with channel AD7. 0 AD7 pin I/O control enabled 1 AD7 pin I/O control disabled 6 ADPC6 ADC Pin Control 6. ADPC6 controls the pin associated with channel AD6. 0 AD6 pin I/O control enabled 1 AD6 pin I/O control disabled 5 ADPC5 ADC Pin Control 5. ADPC5 controls the pin associated with channel AD5.
Analog-to-Digital Converter (S08ADC12V1) Table 10-11. APCTL2 Register Field Descriptions Field Description 7 ADPC15 ADC Pin Control 15. ADPC15 controls the pin associated with channel AD15. 0 AD15 pin I/O control enabled 1 AD15 pin I/O control disabled 6 ADPC14 ADC Pin Control 14. ADPC14 controls the pin associated with channel AD14. 0 AD14 pin I/O control enabled 1 AD14 pin I/O control disabled 5 ADPC13 ADC Pin Control 13. ADPC13 controls the pin associated with channel AD13.
Analog-to-Digital Converter (S08ADC12V1) Table 10-12. APCTL3 Register Field Descriptions Field Description 7 ADPC23 ADC Pin Control 23. ADPC23 controls the pin associated with channel AD23. 0 AD23 pin I/O control enabled 1 AD23 pin I/O control disabled 6 ADPC22 ADC Pin Control 22. ADPC22 controls the pin associated with channel AD22. 0 AD22 pin I/O control enabled 1 AD22 pin I/O control disabled 5 ADPC21 ADC Pin Control 21. ADPC21 controls the pin associated with channel AD21.
Analog-to-Digital Converter (S08ADC12V1) 10.4.1 Clock Select and Divide Control One of four clock sources can be selected as the clock source for the ADC module. This clock source is then divided by a configurable value to generate the input clock to the converter (ADCK). The clock is selected from one of the following sources by means of the ADICLK bits. • The bus clock, which is equal to the frequency at which software is executed. This is the default selection following reset.
Analog-to-Digital Converter (S08ADC12V1) configured for low power operation, long sample time, continuous conversion, and automatic compare of the conversion result to a software determined compare value. 10.4.4.1 Initiating Conversions A conversion is initiated: • Following a write to ADCSC1 (with ADCH bits not all 1s) if software triggered operation is selected. • Following a hardware trigger (ADHWT) event if hardware triggered operation is selected.
Analog-to-Digital Converter (S08ADC12V1) When a conversion is aborted, the contents of the data registers, ADCRH and ADCRL, are not altered. However, they continue to be the values transferred after the completion of the last successful conversion. If the conversion was aborted by a reset, ADCRH and ADCRL return to their reset states. 10.4.4.4 Power Control The ADC module remains in its idle state until a conversion is initiated.
Analog-to-Digital Converter (S08ADC12V1) The maximum total conversion time is determined by the clock source chosen and the divide ratio selected. The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits.
Analog-to-Digital Converter (S08ADC12V1) 10.4.7 MCU Stop3 Mode Operation Stop mode is a low power-consumption standby mode during which most or all clock sources on the MCU are disabled. 10.4.7.1 Stop3 Mode With ADACK Disabled If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a stop instruction aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode.
Analog-to-Digital Converter (S08ADC12V1) NOTE Hexadecimal values designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character. 10.5.1 ADC Module Initialization Example 10.5.1.1 Initialization Sequence Before the ADC module can be used to complete conversions, an initialization procedure must be performed. A typical sequence is as follows: 1.
Analog-to-Digital Converter (S08ADC12V1) ADCCVH/L = 0xxx Holds compare value when compare function enabled APCTL1=0x02 AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins APCTL2=0x00 All other AD pins remain general purpose I/O pins Reset Initialize ADC ADCCFG = 0x98 ADCSC2 = 0x00 ADCSC1 = 0x41 Check COCO=1? No Yes Read ADCRH Then ADCRL To Clear COCO Bit Continue Figure 10-13. Initialization Flowchart for Example 10.
Analog-to-Digital Converter (S08ADC12V1) 10.6.1.1 Analog Supply Pins The ADC module has analog power and ground supplies (VDDAD and VSSAD) available as separate pins on some devices. VSSAD is shared on the same pin as the MCU digital VSS on some devices. On other devices, VSSAD and VDDAD are shared with the MCU digital supply pins.
Analog-to-Digital Converter (S08ADC12V1) For proper conversion, the input voltage must fall between VREFH and VREFL. If the input is equal to or exceeds VREFH, the converter circuit converts the signal to 0xFFF (full scale 12-bit representation), 0x3FF (full scale 10-bit representation) or 0xFF (full scale 8-bit representation). If the input is equal to or less than VREFL, the converter circuit converts it to 0x000. Input voltages between VREFH and VREFL are straight-line linear conversions.
Analog-to-Digital Converter (S08ADC12V1) • — For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces VDD noise but increases effective conversion time due to stop recovery. There is no I/O switching, input or output, on the MCU during the conversion. There are some situations where external system activity causes radiated or conducted noise emissions or excessive VDD noise is coupled into the ADC.
Analog-to-Digital Converter (S08ADC12V1) • • • Differential non-linearity (DNL) — This error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. Integral non-linearity (INL) — This error is defined as the highest-value the (absolute value of the) running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes.
Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1 Introduction The MC9S08JM60 series of microcontrollers has an inter-integrated circuit (IIC) module for communication with other integrated circuits. The two pins associated with this module, SCL and SDA, are shared with PTC0 and PTC1, respectively. NOTE MC9S08JM60 series devices operate at a higher voltage range (2.7 V to 5.5 V) and do not include stop1 mode. Therefore, please disregard references to stop1. MC9S08JM60 Series Data Sheet, Rev.
Chapter 11 Inter-Integrated Circuit (S08IICV2) USBDP USBDN PORT A ON-CHIP ICE AND DEBUG MODULE (DBG) HCS08 CORE USB SIE RESET IRQ/TPMCLK CPU HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP IRQ FULL SPEED USB USB ENDPOINT TRANSCEIVER RAM 8-/16-BIT SERIAL PERIPHERAL INTERFACE MODULE (SPI2) SERIAL COMMUNICATIONS VDDAD IIC MODULE (IIC) SDA SCL 8 4 ACMP– ANALOG COMPARATOR (ACMP) ACMPO VDD VSS VUSB33 LOW-POWER OSCILLATOR SYSTEM VOLTAGE REGULATOR SERIAL COMMU
11.1.
Address Data Bus Interrupt ADDR_DECODE CTRL_REG DATA_MUX FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync Start Stop Arbitration Control Clock Control In/Out Data Shift Register Address Compare SCL SDA Figure 11-2. IIC Functional Block Diagram 11.2 External Signal Description This section describes each user-accessible pin signal. 11.2.1 SCL — Serial Clock Line The bidirectional SCL is the serial clock line of the IIC system. 11.2.
Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.3.1 IIC Address Register (IICA) 7 6 5 4 3 2 1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 0 0 0 0 0 0 0 R 0 0 W Reset 0 = Unimplemented or Reserved Figure 11-3. IIC Address Register (IICA) Table 11-1. IICA Field Descriptions Field Description 7–1 AD[7:1] Slave Address. The AD[7:1] field contains the slave address to be used by the IIC module.
Table 11-2. IICF Field Descriptions Field 7–6 MULT 5–0 ICR Description IIC Multiplier Factor. The MULT bits define the multiplier factor, mul. This factor, along with the SCL divider, generates the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved IIC Clock Rate. The ICR bits are used to prescale the bus clock for bit rate selection.
Table 11-4.
11.3.3 IIC Control Register (IICC1) 7 6 5 4 3 IICEN IICIE MST TX TXAK R W Reset 2 1 0 0 0 0 0 0 RSTA 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-5. IIC Control Register (IICC1) Table 11-5. IICC1 Field Descriptions Field Description 7 IICEN IIC Enable. The IICEN bit determines whether the IIC module is enabled. 0 IIC is not enabled 1 IIC is enabled 6 IICIE IIC Interrupt Enable. The IICIE bit determines whether an IIC interrupt is requested.
Table 11-6. IICS Field Descriptions Field Description 7 TCF Transfer Complete Flag. This bit is set on the completion of a byte transfer. This bit is only valid during or immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by reading the IICD register in receive mode or writing to the IICD in transmit mode. 0 Transfer in progress 1 Transfer complete 6 IAAS Addressed as a Slave.
Table 11-7. IICD Field Descriptions Field Description 7–0 DATA Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data. NOTE When transitioning out of master receive mode, the IIC mode should be switched before reading the IICD register to prevent an inadvertent initiation of a master receive data transfer.
11.4 Functional Description This section provides a complete functional description of the IIC module. 11.4.1 IIC Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent.
11.4.1.2 Slave Address Transmission The first byte of data transferred immediately after the start signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave.
11.4.1.5 Repeated Start Signal As shown in Figure 11-9, a repeated start signal is a start signal generated without first generating a stop signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 11.4.1.6 Arbitration Procedure The IIC bus is a true multi-master bus that allows more than one master to be connected on it.
11.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such a case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 11.4.1.9 Clock Stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer.
After a repeated start condition (Sr), all other slave devices also compare the first seven bits of the first byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them are addressed because R/W = 1 (for 10-bit devices) or the 11110XX slave address (for 7-bit devices) does not match. S Slave Address 1st 7 bits R/W 11110 + AD10 + AD9 0 A1 Slave Address 2nd byte A2 AD[8:1] Sr Slave Address 1st 7 bits R/W 11110 + AD10 + AD9 1 A3 Data A ...
11.6.2 Address Detect Interrupt When the calling address matches the programmed slave address (IIC address register) or when the GCAEN bit is set and a general call is received, the IAAS bit in the status register is set. The CPU is interrupted, provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly. 11.6.3 Arbitration Lost Interrupt The IIC is a true multi-master bus that allows more than one master to be connected on it.
11.7 Initialization/Application Information Module Initialization (Slave) 1. Write: IICC2 — to enable or disable general call — to select 10-bit or 7-bit addressing mode 2. Write: IICA — to set the slave address 3. Write: IICC1 — to enable IIC and interrupts 4. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data 5. Initialize RAM variables used to achieve the routine shown in Figure 11-12 Module Initialization (Master) 1.
Clear IICIF Master Mode ? Y TX N Arbitration Lost ? Y RX Tx/Rx ? N Last Byte Transmitted ? N Clear ARBL Y RXAK=0 ? Last Byte to Be Read ? N N N Y Y IAAS=1 ? Y IAAS=1 ? Y Address Transfer See Note 1 Y End of Addr Cycle (Master Rx) ? Y Y (Read) 2nd Last Byte to Be Read ? N SRW=1 ? Write Next Byte to IICD Set TXACK =1 TX/RX ? Generate Stop Signal (MST = 0) Y Set TX Mode RX TX N (Write) N N Data Transfer See Note 2 ACK from Receiver ? N Switch to Rx Mode Dummy Read fro
MC9S08JM60 Series Data Sheet, Rev.
MC9S08JM60 Series Data Sheet, Rev.
Chapter 12 Multi-Purpose Clock Generator (S08MCGV1) 12.1 Introduction The multi-purpose clock generator (MCG) module provides several clock source choices for the MCU. which contains a frequency-locked loop (FLL) and a phase-locked loop (PLL). The module can select either of the FLL or PLL clocks, or either of the internal or external reference clocks as a source for the MCU system clock.
Chapter 12 Multi-Purpose Clock Generator (S08MCGV1) USBDP USBDN HCS08 CORE PORT A ON-CHIP ICE AND DEBUG MODULE (DBG) USB SIE RESET IRQ/TPMCLK CPU HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT 8-/16-BIT SERIAL PERIPHERAL INTERFACE MODULE (SPI2) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) COP IRQ LVD IIC MODULE (IIC) VDDAD USER Flash (IN BYTES) MC9S08JM60 = 60,912 MC9S08JM32 = 32,768 SS2 SPSCK2 MOSI2 MISO2 RxD2 TxD2 SDA SCL 8 4 ACMP– ANALOG COMPARATOR (ACMP)
Multi-Purpose Clock Generator (S08MCGV1) 12.1.1 Features Key features of the MCG module are: • Frequency-locked loop (FLL) — 0.
Multi-Purpose Clock Generator (S08MCGV1) External Oscillator (XOSC) RANGE EREFS ERCLKEN MCGERCLK HGO EREFSTEN IRCLKEN MCGIRCLK CME IREFSTEN CLKS Clock Monitor LOC BDIV / 2n Internal Reference Clock OSCINIT 9 IREFS MCGOUT n=0-3 LP DCO DCOOUT TRIM PLLS /2 n RDIV_CLK Lock Detector Filter n=0-7 FLL LOLS LOCK MCGFFCLK RDIV LP VCOOUT Phase Detector Charge Pump VDIV Internal Filter MCGLCLK /2 VCO PLL /(4,8,12,...,40) Multi-purpose Clock Generator (MCG) Figure 12-2.
Multi-Purpose Clock Generator (S08MCGV1) 12.1.2 Modes of Operation There are nine modes of operation for the MCG: • FLL Engaged Internal (FEI) • FLL Engaged External (FEE) • FLL Bypassed Internal (FBI) • FLL Bypassed External (FBE) • PLL Engaged External (PEE) • PLL Bypassed External (PBE) • Bypassed Low Power Internal (BLPI) • Bypassed Low Power External (BLPE) • Stop For details see Section 12.4.1, “Operational Modes.” 12.2 External Signal Description There are no MCG signals that connect off chip.
Multi-Purpose Clock Generator (S08MCGV1) 12.3 Register Definition 12.3.1 MCG Control Register 1 (MCGC1) 7 6 5 4 3 2 1 0 IREFS IRCLKEN IREFSTEN 1 0 0 R CLKS RDIV W Reset: 0 0 0 0 0 Figure 12-3. MCG Control Register 1 (MCGC1) Table 12-1. MCG Control Register 1 Field Descriptions Field Description 7:6 CLKS Clock Source Select — Selects the system clock source. 00 Encoding 0 — Output of FLL or PLL is selected. 01 Encoding 1 — Internal reference clock is selected.
Multi-Purpose Clock Generator (S08MCGV1) 12.3.2 MCG Control Register 2 (MCGC2) 7 6 5 4 3 2 RANGE HGO LP EREFS 0 0 0 0 1 0 R BDIV ERCLKEN EREFSTEN W Reset: 0 1 0 0 Figure 12-4. MCG Control Register 2 (MCGC2) Table 12-2. MCG Control Register 2 Field Descriptions Field Description 7:6 BDIV Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits in the MCGC1 register. This controls the bus frequency.
Multi-Purpose Clock Generator (S08MCGV1) 12.3.3 MCG Trim Register (MCGTRM) 7 6 5 4 3 2 1 0 R TRIM W POR: 1 0 0 0 0 0 0 0 Reset: U U U U U U U U Figure 12-5. MCG Trim Register (MCGTRM) Table 12-3. MCG Trim Register Field Descriptions Field Description 7:0 TRIM MCG Trim Setting — Controls the internal reference clock frequency by controlling the internal reference clock period. The TRIM bits are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Multi-Purpose Clock Generator (S08MCGV1) 12.3.4 MCG Status and Control Register (MCGSC) R 7 6 5 4 3 LOLS LOCK PLLST IREFST 2 CLKST 1 0 OSCINIT FTRIM W POR: Reset: 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 U Figure 12-6. MCG Status and Control Register (MCGSC) Table 12-4. MCG Status and Control Register Field Descriptions Field Description 7 LOLS Loss of Lock Status — This bit is a sticky indication of lock status for the FLL or PLL.
Multi-Purpose Clock Generator (S08MCGV1) Table 12-4. MCG Status and Control Register Field Descriptions (continued) Field Description 1 OSCINIT OSC Initialization — If the external reference clock is selected by ERCLKEN or by the MCG being in FEE, FBE, PEE, PBE, or BLPE mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator clock have completed.
Multi-Purpose Clock Generator (S08MCGV1) Table 12-5. MCG PLL Register Field Descriptions (continued) Field Description 5 CME Clock Monitor Enable — Determines if a reset request is made following a loss of external clock indication. The CME bit should only be set to a logic 1 when either the MCG is in an operational mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE) or the external reference is enabled (ERCLKEN=1 in the MCGC2 register).
Multi-Purpose Clock Generator (S08MCGV1) 12.4 Functional Description 12.4.
Multi-Purpose Clock Generator (S08MCGV1) In FLL engaged internal mode, the MCGOUT clock is derived from the FLL clock, which is controlled by the internal reference clock. The FLL clock frequency locks to 1024 times the reference frequency, as selected by the RDIV bits. The MCGLCLK is derived from the FLL and the PLL is disabled in a low power state. 12.4.1.
Multi-Purpose Clock Generator (S08MCGV1) • • • • • CLKS bits are written to 10 IREFS bit is written to 0 PLLS bit is written to 0 RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz LP bit is written to 0 In FLL bypassed external mode, the MCGOUT clock is derived from the external reference clock. The external reference clock which is enabled can be an external crystal/resonator or it can be another external clock source.
Multi-Purpose Clock Generator (S08MCGV1) 12.4.1.6 PLL Bypassed External (PBE) In PLL bypassed external (PBE) mode, the MCGOUT clock is derived from the external reference clock and the PLL is operational but its output clock is not used. This mode is useful to allow the PLL to acquire its target frequency while the MCGOUT clock is driven from the external reference clock.
Multi-Purpose Clock Generator (S08MCGV1) In bypassed low power external mode, the MCGOUT clock is derived from the external reference clock. The external reference clock which is enabled can be an external crystal/resonator or it can be another external clock source. The PLL and the FLL are disabled at all times in BLPE mode and the MCGLCLK will not be available for BDC communications.
Multi-Purpose Clock Generator (S08MCGV1) 12.4.4 Low Power Bit Usage The low power bit (LP) is provided to allow the FLL or PLL to be disabled and thus conserve power when these systems are not being used. However, in some applications it may be desirable to enable the FLL or PLL and allow it to lock for maximum accuracy before switching to an engaged mode. Do this by writing the LP bit to 0. 12.4.
Multi-Purpose Clock Generator (S08MCGV1) • BDIV=00 (divide by 1), RDIV < 010 BDIV=01 (divide by 2), RDIV < 011 12.5 Initialization / Application Information This section describes how to initialize and configure the MCG module in application. The following sections include examples on how to initialize the MCG and properly switch between the various available modes. 12.5.1 MCG Module Initialization Sequence The MCG comes out of reset configured for FEI mode with the BDIV set for divide-by-2.
Multi-Purpose Clock Generator (S08MCGV1) minimum power consumption, leave the internal reference disabled while in an external clock mode. 3. After the proper configuration bits have been set, wait for the affected bits in the MCGSC register to be changed appropriately, reflecting that the MCG has moved into the proper mode.
Multi-Purpose Clock Generator (S08MCGV1) The table below shows MCGOUT frequency calculations using RDIV, BDIV, and VDIV settings for each clock mode. The bus frequency is equal to MCGOUT divided by 2. Table 12-6. MCGOUT Frequency Calculation Options fMCGOUT1 Clock Mode Note FEI (FLL engaged internal) (fint * 1024) / B Typical fMCGOUT = 16 MHz immediately after reset. RDIV bits set to %000. FEE (FLL engaged external) (fext / R *1024) / B fext / R must be in the range of 31.25 kHz to 39.
Multi-Purpose Clock Generator (S08MCGV1) c) MCGC1 = 0xB8 (%10111000) – CLKS (bits 7 and 6) set to %10 in order to select external reference clock as system clock source – RDIV (bits 5-3) set to %111, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is in the 31.25 kHz to 39.
Multi-Purpose Clock Generator (S08MCGV1) START IN FEI MODE MCGC2 = $36 IN BLPE MODE ? (LP=1) CHECK NO NO YES OSCINIT = 1 ? MCGC2 = $36 (LP = 0) YES MCGC1 = $B8 CHECK PLLST = 1? CHECK NO NO YES IREFST = 0? YES CHECK LOCK = 1? CHECK CLKST = %10? NO NO YES MCGC1 = $10 YES ENTER BLPE MODE ? NO CHECK CLKST = %11? NO YES YES MCGC2 = $3E (LP = 1) CONTINUE IN PEE MODE MCGC1 = $90 MCGC3 = $44 Figure 12-9.
Multi-Purpose Clock Generator (S08MCGV1) 12.5.2.2 Example # 2: Moving from PEE to BLPI Mode: External Crystal = 4 MHz, Bus Frequency =16 kHz In this example, the MCG will move through the proper operational modes from PEE mode with a 4 MHz crystal configured for an 8 MHz bus frequency (see previous example) to BLPI mode with a 16 kHz bus frequency.First, the code sequence will be described. Then a flowchart will be included which illustrates the sequence. 1.
Multi-Purpose Clock Generator (S08MCGV1) 4. Lastly, FBI transitions into FBILP mode. a) MCGC2 = 0x08 (%00001000) – LP (bit 3) in MCGSC is 1 START IN PEE MODE MCGC1 = $90 CHECK PLLST = 0? CHECK NO CLKST = %10 ? YES YES OPTIONAL: CHECK LOCK = 1? ENTER NO NO NO BLPE MODE ? YES MCGC1 = $44 YES MCGC2 = $3E CHECK IREFST = 0? MCGC1 = $B8 MCGC3 = $04 IN BLPE MODE ? (LP=1) NO YES NO CHECK CLKST = %01? NO YES YES MCGC2 = $36 (LP = 0) MCGC2 = $08 CONTINUE IN BLPI MODE Figure 12-10.
Multi-Purpose Clock Generator (S08MCGV1) 12.5.2.3 Example #3: Moving from BLPI to FEE Mode: External Crystal = 4 MHz, Bus Frequency = 16 MHz In this example, the MCG will move through the proper operational modes from BLPI mode at a 16 kHz bus frequency running off of the internal reference clock (see previous example) to FEE mode using a 4 MHz crystal configured for a 16 MHz bus frequency. First, the code sequence will be described. Then a flowchart will be included which illustrates the sequence. 1.
Multi-Purpose Clock Generator (S08MCGV1) START IN BLPI MODE CHECK NO IREFST = 0? MCGC2 = $00 YES OPTIONAL: CHECK LOCK = 1? NO OPTIONAL: CHECK LOCK = 1? NO YES YES MCGC2 = $36 CHECK CLKST = %00? CHECK NO NO YES OSCINIT = 1 ? CONTINUE YES IN FEE MODE MCGC1 = $38 Figure 12-11. Flowchart of BLPI to FEE Mode Transition using a 4 MHz Crystal 12.5.2.
Multi-Purpose Clock Generator (S08MCGV1) external crystal and a maximum reference divider factor of 128, the resulting frequency of the reference clock for the FLL is 62.5 kHz (greater than the 39.0625 kHz maximum allowed). Care must be taken in the software to minimize the amount of time spent in this state where the FLL is operating in this condition.
Multi-Purpose Clock Generator (S08MCGV1) c) MCGC1 = 0x98 (%10011000) – RDIV (bits 5-3) set to %011, or divide-by-8 because 8 MHz / 8= 1 MHz which is in the 1 MHz to 2 MHz range required by the PLL. In BLPE mode, the configuration of the RDIV does not matter because both the FLL and PLL are disabled. Changing them only sets up the the dividers for PLL usage in PBE mode d) MCGC3 = 0x44 (%01000100) – PLLS (bit 6) set to 1, selects the PLL.
Multi-Purpose Clock Generator (S08MCGV1) START IN FEI MODE MCGC2 = $36 CHECK NO CHECK PLLST = 1? NO OSCINIT = 1 ? YES YES MCGC2 = $36 (LP = 0) MCGC1 = $B8 CHECK NO IREFST = 0? CHECK LOCK = 1? NO YES YES CHECK CLKST = %10? NO MCGC1 = $18 YES CHECK CLKST = %11? MCGC2 = $3E (LP = 1) NO YES MCGC1 = $98 MCGC3 = $44 CONTINUE IN PEE MODE Figure 12-12. Flowchart of FEI to PEE Mode Transition using a 8 MHz Crystal MC9S08JM60 Series Data Sheet, Rev.
Multi-Purpose Clock Generator (S08MCGV1) 12.5.3 Calibrating the Internal Reference Clock (IRC) The IRC is calibrated by writing to the MCGTRM register first, then using the FTRIM bit to “fine tune” the frequency. We will refer to this total 9-bit value as the trim value, ranging from 0x000 to 0x1FF, where the FTRIM bit is the LSB. The trim value after a POR is always 0x100 (MCGTRM = 0x80 and FTRIM = 0). Writing a larger value will decrease the frequency and smaller values will increase the frequency.
Multi-Purpose Clock Generator (S08MCGV1) Initial conditions: 1) Clock supplied from ATE has 500 μs duty period 2) MCG configured for internal reference with 8MHz bus START TRIM PROCEDURE TRMVAL = $100 n=1 MEASURE INCOMING CLOCK WIDTH (COUNT = # OF BUS CLOCKS / 8) COUNT < EXPECTED = 500 (RUNNING TOO SLOW) .
Multi-Purpose Clock Generator (S08MCGV1) MC9S08JM60 Series Data Sheet, Rev.
Chapter 13 Real-Time Counter (S08RTCV1) 13.1 Introduction The real-time counter (RTC) consists of one 8-bit counter, one 8-bit comparator, several binary-based and decimal-based prescaler dividers, two clock sources, and one programmable periodic interrupt. This module can be used for time-of-day, calendar or any task scheduling functions. It can also serve as a cyclic wake up from low power modes without the need of external components. MC9S08JM60 Series Data Sheet, Rev.
Chapter 13 Real-Time Counter (S08RTCV1) USBDP USBDN HCS08 CORE PORT A ON-CHIP ICE AND DEBUG MODULE (DBG) USB SIE RESET IRQ/TPMCLK CPU HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT 8-/16-BIT SERIAL PERIPHERAL INTERFACE MODULE (SPI2) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) COP IRQ LVD IIC MODULE (IIC) VDDAD USER Flash (IN BYTES) MC9S08JM60 = 60,912 MC9S08JM32 = 32,768 SS2 SPSCK2 MOSI2 MISO2 RxD2 TxD2 SDA SCL 8 4 ACMP– ANALOG COMPARATOR (ACMP) ACMPO VDD
Real-Time Counter (S08RTCV1) 13.1.1 Features Features of the RTC module include: • 8-bit up-counter — 8-bit modulo match limit — Software controllable periodic interrupt on match • Three software selectable clock sources for input to prescaler with selectable binary-based and decimal-based divider values — 1 kHz internal low-power oscillator (LPO) — External clock (ERCLK) — 32 kHz internal clock (IRCLK) 13.1.
Real-Time Counter (S08RTCV1) 13.1.3 Block Diagram The block diagram for the RTC module is shown in Figure 13-2. LPO Clock Source Select ERCLK IRCLK 8-Bit Modulo (RTCMOD) RTCLKS VDD RTCLKS[0] RTCPS Prescaler Divide-By Q D Background Mode E 8-Bit Comparator RTC Clock RTC Interrupt Request RTIF R Write 1 to RTIF 8-Bit Counter (RTCCNT) RTIE Figure 13-2. Real-Time Counter (RTC) Block Diagram 13.2 External Signal Description The RTC does not include any off-chip signals. 13.
Real-Time Counter (S08RTCV1) 13.3.1 RTC Status and Control Register (RTCSC) RTCSC contains the real-time interrupt status flag (RTIF), the clock select bits (RTCLKS), the real-time interrupt enable bit (RTIE), and the prescaler select bits (RTCPS). 7 6 5 4 3 2 1 0 0 0 R RTIF RTCLKS RTIE RTCPS W Reset: 0 0 0 0 0 0 Figure 13-3. RTC Status and Control Register (RTCSC) Table 13-2.
Real-Time Counter (S08RTCV1) 13.3.2 RTC Counter Register (RTCCNT) RTCCNT is the read-only value of the current RTC count of the 8-bit counter. 7 6 5 4 R 3 2 1 0 0 0 0 0 RTCCNT W Reset: 0 0 0 0 Figure 13-4. RTC Counter Register (RTCCNT) Table 13-4. RTCCNT Field Descriptions Field Description 7:0 RTCCNT RTC Count. These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to this register.
Real-Time Counter (S08RTCV1) RTCPS and the RTCLKS[0] bit select the desired divide-by value. If a different value is written to RTCPS, the prescaler and RTCCNT counters are reset to 0x00. Table 13-6 shows different prescaler period values. Table 13-6. Prescaler Period RTCPS 1-kHz Internal Clock (RTCLKS = 00) 1-MHz External Clock 32-kHz Internal Clock 32-kHz Internal Clock (RTCLKS = 01) (RTCLKS = 10) (RTCLKS = 11) 0000 Off Off Off Off 0001 8 ms 1.024 ms 250 μs 32 ms 0010 32 ms 2.
Real-Time Counter (S08RTCV1) Internal 1-kHz Clock Source RTC Clock (RTCPS = 0xA) RTCCNT 0x52 0x53 0x54 0x55 0x00 0x01 RTIF RTCMOD 0x55 Figure 13-6. RTC Counter Overflow Example In the example of Figure 13-6, the selected clock source is the 1-kHz internal oscillator clock source. The prescaler (RTCPS) is set to 0xA or divide-by-4. The modulo value in the RTCMOD register is set to 0x55.
Real-Time Counter (S08RTCV1) RTCSC.byte = RTCSC.byte | 0x80; /* RTC interrupts every 1 Second */ Seconds++; /* 60 seconds in a minute */ if (Seconds > 59){ Minutes++; Seconds = 0; } /* 60 minutes in an hour */ if (Minutes > 59){ Hours++; Minutes = 0; } /* 24 hours in a day */ if (Hours > 23){ Days ++; Hours = 0; } MC9S08JM60 Series Data Sheet, Rev.
Real-Time Counter (S08RTCV1) MC9S08JM60 Series Data Sheet, Rev.
Chapter 14 Serial Communications Interface (S08SCIV4) 14.1 Introduction The MC9S08JM60 series include two independent serial communications interface (SCI) modules which are sometimes called universal asynchronous receiver/transmitters (UARTs). Typically, these systems are used to connect to the RS232 serial input/output (I/O) port of a personal computer or workstation, but they can also be used to communicate with other embedded controllers.
Chapter 14 Serial Communications Interface (S08SCIV4) USBDP USBDN HCS08 CORE PORT A ON-CHIP ICE AND DEBUG MODULE (DBG) USB SIE RESET IRQ/TPMCLK CPU HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT 8-/16-BIT SERIAL PERIPHERAL INTERFACE MODULE (SPI2) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) COP IRQ LVD IIC MODULE (IIC) VDDAD USER Flash (IN BYTES) MC9S08JM60 = 60,912 MC9S08JM32 = 32,768 SS2 SPSCK2 MOSI2 MISO2 RxD2 TxD2 SDA SCL 8 4 ACMP– ANALOG COMPARATOR (ACM
Serial Communications Interface (S08SCIV4) 14.1.
Serial Communications Interface (S08SCIV4) 14.1.3 Block Diagram Figure 14-2 shows the transmitter portion of the SCI.
Serial Communications Interface (S08SCIV4) Figure 14-3 shows the receiver portion of the SCI.
Serial Communications Interface (S08SCIV4) 14.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names.
Serial Communications Interface (S08SCIV4) 7 6 5 4 3 2 1 0 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0 0 0 0 0 1 0 0 R W Reset Figure 14-5. SCI Baud Rate Register (SCIxBDL) Table 14-2. SCIxBDL Field Descriptions Field 7:0 SBR[7:0] 14.2.2 Description Baud Rate Modulo Divisor — These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the SCI baud rate generator.
Serial Communications Interface (S08SCIV4) Table 14-3. SCIxC1 Field Descriptions (continued) Field 3 WAKE Description Receiver Wakeup Method Select — Refer to Section 14.3.3.2, “Receiver Wakeup Operation” for more information. 0 Idle-line wakeup. 1 Address-mark wakeup. 2 ILT Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic.
Serial Communications Interface (S08SCIV4) Table 14-4. SCIxC2 Field Descriptions (continued) Field Description 3 TE Transmitter Enable 0 Transmitter off. 1 Transmitter on. TE must be 1 in order to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output for the SCI system. When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of traffic on the single SCI communication line (TxD pin).
Serial Communications Interface (S08SCIV4) Table 14-5. SCIxS1 Field Descriptions Field Description 7 TDRE Transmit Data Register Empty Flag — TDRE is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCIxS1 with TDRE = 1 and then write to the SCI data register (SCIxD). 0 Transmit data register (buffer) full. 1 Transmit data register (buffer) empty.
Serial Communications Interface (S08SCIV4) Table 14-5. SCIxS1 Field Descriptions (continued) Field Description 1 FE Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIxS1 with FE = 1 and then read the SCI data register (SCIxD). 0 No framing error detected. This does not guarantee the framing is correct. 1 Framing error.
Serial Communications Interface (S08SCIV4) Table 14-6. SCIxS2 Field Descriptions (continued) 1 Field Description 1 LBKDE LIN Break Detection Enable— LBKDE is used to select a longer break character detection length. While LBKDE is set, framing error (FE) and receive data register full (RDRF) flags are prevented from setting. 0 Break character is detected at length of 10 bit times (11 if M = 1). 1 Break character is detected at length of 11 bit times (12 if M = 1).
Serial Communications Interface (S08SCIV4) Table 14-7. SCIxC3 Field Descriptions (continued) Field 4 TXINV1 1 Description Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output. 0 Transmit data not inverted 1 Transmit data inverted 3 ORIE Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests. 0 OR interrupts disabled (use polling). 1 Hardware interrupt requested when OR = 1.
Serial Communications Interface (S08SCIV4) MODULO DIVIDE BY (1 THROUGH 8191) BUSCLK SBR12:SBR0 BAUD RATE GENERATOR OFF IF [SBR12:SBR0] = 0 DIVIDE BY 16 Tx BAUD RATE Rx SAMPLING CLOCK (16 × BAUD RATE) BAUD RATE = BUSCLK [SBR12:SBR0] × 16 Figure 14-12. SCI Baud Rate Generation SCI communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the same baud rate.
Serial Communications Interface (S08SCIV4) Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity that is in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters. 14.3.2.1 Send Break and Queued Idle The SBK control bit in SCIxC2 is used to send break characters which were originally used to gain the attention of old teletype receivers.
Serial Communications Interface (S08SCIV4) status flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver overrun.
Serial Communications Interface (S08SCIV4) message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next message. 14.3.3.2.1 Idle-Line Wakeup When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared automatically when the receiver detects a full character time of the idle-line level.
Serial Communications Interface (S08SCIV4) Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status flags if the corresponding TIE or TCIE local interrupt masks are 0s. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF = 1 and then reading SCIxD.
Serial Communications Interface (S08SCIV4) 14.3.5.2 Stop Mode Operation During all stop modes, clocks to the SCI module are halted. In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these two stop modes. No SCI module registers are affected in stop3 mode. The receive input active edge detect circuit is still active in stop3 mode, but not in stop2..
Serial Communications Interface (S08SCIV4) MC9S08JM60 Series Data Sheet, Rev.
Chapter 15 16-Bit Serial Peripheral Interface (S08SPI16V1) 15.1 Introduction The 8- or 16-bit selectable serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial communication between the MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, memories, etc. The SPI runs at a baud rate up to the bus clock divided by two in master mode and up to the bus clock divided by four in slave mode.
Chapter 15 16-Bit Serial Peripheral Interface (S08SPI16V1) USBDP USBDN HCS08 CORE PORT A ON-CHIP ICE AND DEBUG MODULE (DBG) USB SIE RESET IRQ/TPMCLK CPU HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT 8-/16-BIT SERIAL PERIPHERAL INTERFACE MODULE (SPI2) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) COP IRQ LVD IIC MODULE (IIC) VDDAD USER Flash (IN BYTES) MC9S08JM60 = 60,912 MC9S08JM32 = 32,768 SS2 SPSCK2 MOSI2 MISO2 RxD2 TxD2 SDA SCL 8 4 ACMP– ANALOG COMPARATOR
Serial Peripheral Interface (S08SPI16V1) Module Initialization (Slave): Write: SPIxC1 to configure interrupts, set primary SPI options, slave mode select, and system enable. Write: SPIxC2 to configure optional SPI features, hardware match interrupt enable, and 8- or 16-bit data transmission length Write: SPIxMH:SPIxML to set hardware compare value that triggers SPMF (optional) when value in receive data buffer equals this value.
Serial Peripheral Interface (S08SPI16V1) 15.1.
Serial Peripheral Interface (S08SPI16V1) 15.1.4.1 SPI System Block Diagram Figure 15-3 shows the SPI modules of two MCUs connected in a master-slave arrangement. The master device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively exchanges the data that was in the SPI shift registers of the two SPI systems.
Serial Peripheral Interface (S08SPI16V1) PIN CONTROL M SPE MOSI (MOMI) S Tx BUFFER (WRITE SPIxDH:SPIxDL) ENABLE SPI SYSTEM M SHIFT OUT SPIMODE 8 OR 16 BIT MODE SHIFT IN SPI SHIFT REGISTER MISO (SISO) S SPC0 Rx BUFFER (READ SPIxDH:SPIxDL) BIDIROE LSBFE SHIFT DIRECTION SHIFT CLOCK Rx BUFFER FULL Tx BUFFER EMPTY MASTER CLOCK BUS RATE CLOCK SPIBR CLOCK GENERATOR MSTR CLOCK LOGIC SLAVE CLOCK MASTER/SLAVE M SPSCK S MASTER/ SLAVE MODE SELECT MODFEN SSOE MODE FAULT DETECTION 16-BIT COMPA
Serial Peripheral Interface (S08SPI16V1) 15.2.2 MOSI — Master Data Out, Slave Data In When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data output. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data input. If SPC0 = 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes the bidirectional data I/O pin (MOMI).
Serial Peripheral Interface (S08SPI16V1) Table 15-1. SPIxC1 Field Descriptions Field Description 7 SPIE SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF) and mode fault (MODF) events. 0 Interrupts from SPRF and MODF inhibited (use polling) 1 When SPRF or MODF is 1, request a hardware interrupt 6 SPE SPI System Enable — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions.
Serial Peripheral Interface (S08SPI16V1) 7 6 5 SPMIE SPIMODE 0 0 R 4 3 MODFEN BIDIROE 0 0 0 2 1 0 SPISWAI SPC0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 15-6. SPI Control Register 2 (SPIxC2) Table 15-3. SPIxC2 Register Field Descriptions Field 7 SPMIE Description SPI Match Interrupt Enable — This is the interrupt enable for the SPI receive data buffer hardware match (SPMF) function. 0 Interrupts from SPMF inhibited (use polling).
Serial Peripheral Interface (S08SPI16V1) Table 15-4. Bidirectional Pin Configurations Pin Mode SPC0 BIDIROE MISO MOSI Master Mode of Operation Normal 0 X Master In Master Out Bidirectional 1 0 MISO not used by SPI Master In 1 Master I/O Slave Mode of Operation 15.3.3 Normal 0 X Slave Out Slave In Bidirectional 1 0 Slave In MOSI not used by SPI 1 Slave I/O SPI Baud Rate Register (SPIxBR) This register is used to set the prescaler and bit rate divisor for an SPI master.
Serial Peripheral Interface (S08SPI16V1) Table 15-6. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 Prescaler Divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 Table 15-7. SPI Baud Rate Divisor 15.3.4 SPR2:SPR1:SPR0 Rate Divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 SPI Status Register (SPIxS) This register has four read-only status bits. Bits 3 through 0 are not implemented and always read 0.
Serial Peripheral Interface (S08SPI16V1) Table 15-8. SPIxS Register Field Descriptions Field Description 7 SPRF SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data register (SPIxDH:SPIxDL). SPRF is cleared by reading SPRF while it is set, then reading the SPI data register. 0 No data available in the receive data buffer. 1 Data available in the receive data buffer.
Serial Peripheral Interface (S08SPI16V1) When the SPI is configured as a master, data queued in the transmit data buffer is transmitted immediately after the previous transmission has completed. The SPI transmit buffer empty flag (SPTEF) in the SPIxS register indicates when the transmit data buffer is ready to accept new data. SPIxS must be read when SPTEF is set before writing to the SPI data registers, or the write will be ignored.
Serial Peripheral Interface (S08SPI16V1) 15.4 15.4.1 Functional Description General The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1.
Serial Peripheral Interface (S08SPI16V1) and SPSCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs are disabled and SPSCK, MOSI and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state.
Serial Peripheral Interface (S08SPI16V1) NOTE When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line. As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves.
Serial Peripheral Interface (S08SPI16V1) Any switching between 8- and 16-bit data transmission length (controlled by SPIMODE bit) in master mode will abort a transmission in progress, force the SPI system into idle state, and reset all status bits in the SPIxS register. To initiate a transfer after writing to SPIMODE, the SPIxS register must be read with SPTEF = 1, and data must be written to SPIxDH:SPIxDL in 16-bit mode (SPIMODE = 1) or SPIxDL in 8-bit mode (SPIMODE = 0).
Serial Peripheral Interface (S08SPI16V1) BIT TIME # (REFERENCE) 1 2 ... 6 7 8 BIT 7 BIT 0 BIT 6 BIT 1 ... ... BIT 2 BIT 5 BIT 1 BIT 6 BIT 0 BIT 7 SPSCK (CPOL = 0) SPSCK (CPOL = 1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST LSB FIRST MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure 15-13. SPI Clock Formats (CPHA = 1) When CPHA = 1, the slave begins to drive its MISO output when SS goes to active low, but the data is not defined until the first SPSCK edge.
Serial Peripheral Interface (S08SPI16V1) SPSCK cycle after the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 BIT 7 BIT 0 BIT 6 BIT 1 ... 6 7 8 BIT 2 BIT 5 BIT 1 BIT 6 BIT 0 BIT 7 SPSCK (CPOL = 0) SPSCK (CPOL = 1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST LSB FIRST ... ... MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure 15-14.
Serial Peripheral Interface (S08SPI16V1) The baud rate divisor equation is as follows: BaudRateDivisor = ( SPPR + 1 ) • 2 ( SPR + 1 ) The baud rate can be calculated with the following equation: Baud Rate = BusClock ⁄ BaudRateDivisor BUS CLOCK PRESCALER BAUD RATE DIVIDER DIVIDE BY 1, 2, 3, 4, 5, 6, 7, or 8 DIVIDE BY 2, 4, 8, 16, 32, 64, 128, or 256 SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 MASTER SPI BIT RATE Figure 15-15. SPI Baud Rate Generation 15.4.7 15.4.7.
Serial Peripheral Interface (S08SPI16V1) Table 15-9. Normal Mode and Bidirectional Mode When SPE = 1 Master Mode MSTR = 1 Serial Out Normal Mode SPC0 = 0 SPI SPI Serial Out MISO Serial Out SPI MOSI Serial In MOSI Serial In Bidirectional Mode SPC0 = 1 Slave Mode MSTR = 0 MOMI MISO Serial In BIDIROE SPI BIDIROE Serial In Serial Out SISO . The direction of each serial I/O pin depends on the BIDIROE bit.
Serial Peripheral Interface (S08SPI16V1) In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur in slave mode. If a mode fault error occurs the SPI is switched to slave mode, with the exception that the slave output buffer is disabled.
Serial Peripheral Interface (S08SPI16V1) NOTE Care must be taken when expecting data from a master while the slave is in wait or stop3 mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e. a SPRF interrupt will not be generated until exiting stop or wait mode). Also, the data from the shift register will not be copied into the SPIxDH:SPIxDL registers until after the slave SPI has exited wait or stop mode.
Serial Peripheral Interface (S08SPI16V1) the flag bits to determine what event caused the interrupt. The service routine should also clear the flag bit(s) before returning from the ISR (usually near the beginning of the ISR). 15.4.10.1 MODF MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see Table 15-2). Once MODF is set, the current transfer is aborted and the following bit is changed: • MSTR=0, The master bit in SPIxC1 resets.
Serial Peripheral Interface (S08SPI16V1) 15.5 Initialization/Application Information 15.5.1 SPI Module Initialization Example 15.5.1.1 Initialization Sequence Before the SPI module can be used for communication, an initialization procedure must be carried out, as follows: 1. Update control register 1 (SPIxC1) to enable the SPI and to control interrupt enables. This register also sets the SPI as master or slave, determines clock phase and polarity, and configures the main SPI options. 2.
Serial Peripheral Interface (S08SPI16V1) SPIxC2 = 0xC0(%11000000) Bit 7 SPMIE = 1 SPI hardware match interrupt enabled Bit 6 SPIMODE = 1 Configures SPI for 16-bit mode = 0 Unimplemented = 0 Disables mode fault function Bit 5 Bit 4 MODFEN Bit 3 BIDIROE Bit 2 = 0 SPI data I/O pin acts as input = 0 Unimplemented Bit 1 SPISWAI = 0 SPI clocks operate in wait mode Bit 0 SPC0 = 0 uses separate pins for data input and output SPIxBR = 0x00(%00000000) Bit 7 = 0 Unimplemented Bit 6:4
Serial Peripheral Interface (S08SPI16V1) RESET INITIALIZE SPI SPIxC1 = 0x54 SPIxC2 = 0xC0 SPIxBR = 0x00 SPIxMH = 0xXX YES SPTEF = 1 ? NO YES WRITE TO SPIxDH:SPIxDL SPRF = 1 ? NO YES READ SPIxDH:SPIxDL SPMF = 1 ? NO YES READ SPMF WHILE SET TO CLEAR FLAG, THEN WRITE A 1 TO IT CONTINUE Figure 15-16. Initialization Flowchart Example for SPI Master Device in 16-bit Mode MC9S08JM60 Series Data Sheet, Rev.
Serial Peripheral Interface (S08SPI16V1) MC9S08JM60 Series Data Sheet, Rev.
Chapter 16 Timer/Pulse-Width Modulator (S08TPMV3) 16.1 Introduction The MC9S08JM60 series includes two independent timer/PWM (TPM) modules which support traditional input capture, output compare, or buffered edge-aligned pulse-width modulation (PWM) on each channel. A control bit in each TPM configures all channels in that timer to operate as center-aligned PWM functions.
Chapter 16 Timer/Pulse-Width Modulator (S08TPMV3) USBDP USBDN HCS08 CORE PORT A ON-CHIP ICE AND DEBUG MODULE (DBG) USB SIE RESET IRQ/TPMCLK CPU HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT 8-/16-BIT SERIAL PERIPHERAL INTERFACE MODULE (SPI2) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) COP IRQ LVD IIC MODULE (IIC) VDDAD USER Flash (IN BYTES) MC9S08JM60 = 60,912 MC9S08JM32 = 32,768 SS2 SPSCK2 MOSI2 MISO2 RxD2 TxD2 SDA SCL 8 4 ACMP– ANALOG COMPARATOR (ACMP)
Timer/PWM Module (S08TPMV3) 16.1.
Timer/PWM Module (S08TPMV3) • • Edge-aligned PWM mode The value of a 16-bit modulo register plus 1 sets the period of the PWM output signal. The channel value register sets the duty cycle of the PWM output signal. The user may also choose the polarity of the PWM output signal. Interrupts are available at the end of the period and at the duty-cycle transition point.
Timer/PWM Module (S08TPMV3) BUS CLOCK FIXED SYSTEM CLOCK SYNC EXTERNAL CLOCK CLOCK SOURCE SELECT OFF, BUS, FIXED SYSTEM CLOCK, EXT PRESCALE AND SELECT ³1, 2, 4, 8, 16, 32, 64, or ³128 CLKSB:CLKSA PS2:PS1:PS0 CPWMS 16-BIT COUNTER TOF COUNTER RESET TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TPMxMODH:TPMxMODL CHANNEL 0 ELS0B ELS0A PORT LOGIC TPMxCH0 16-BIT COMPARATOR TPMxC0VH:TPMxC0VL CH0F INTERNAL BUS 16-BIT LATCH CHANNEL 1 MS0B MS0A ELS1B ELS1A CH0IE INTERRUPT LOGIC PORT LOGIC TPMx
Timer/PWM Module (S08TPMV3) The TPM channels are programmable independently as input capture, output compare, or edge-aligned PWM channels. Alternately, the TPM can be configured to produce CPWM outputs on all channels. When the TPM is configured for CPWMs, the counter operates as an up/down counter; input capture, output compare, and EPWM functions are not practical. If a channel is configured as input capture, an internal pullup device may be enabled for that channel.
Timer/PWM Module (S08TPMV3) 16.2.1.1 EXTCLK — External Clock Source Control bits in the timer status and control register allow the user to select nothing (timer disable), the bus-rate clock (the normal default source), a crystal-related clock, or an external clock as the clock which drives the TPM prescaler and subsequently the 16-bit TPM counter. The external clock source is synchronized in the TPM.
Timer/PWM Module (S08TPMV3) When a channel is configured for edge-aligned PWM (CPWMS=0, MSnB=1 and ELSnB:ELSnA not = 0:0), the data direction is overridden, the TPMxCHn pin is forced to be an output controlled by the TPM, and ELSnA controls the polarity of the PWM output signal on the pin. When ELSnB:ELSnA=1:0, the TPMxCHn pin is forced high at the start of each new period (TPMxCNT=0x0000), and the pin is forced low when the channel value register matches the timer counter.
Timer/PWM Module (S08TPMV3) When the TPM is configured for center-aligned PWM (and ELSnB:ELSnA not = 0:0), the data direction for all channels in this TPM are overridden, the TPMxCHn pins are forced to be outputs controlled by the TPM, and the ELSnA bits control the polarity of each TPMxCHn output.
Timer/PWM Module (S08TPMV3) 16.3 Register Definition This section consists of register descriptions in address order. A typical MCU system may contain multiple TPMs, and each TPM may have one to eight channels, so register names include placeholder characters to identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n. TPM1C2SC would be the status and control register for channel 2 of timer 1. 16.3.
Timer/PWM Module (S08TPMV3) Table 16-2. TPMxSC Field Descriptions (continued) Field Description 4–3 Clock source selects. As shown in Table 16-3, this 2-bit field is used to disable the TPM system or select one of CLKS[B:A] three clock sources to drive the counter prescaler. The fixed system clock source is only meaningful in systems with a PLL-based system clock. When there is no PLL, the fixed-system clock source is the same as the bus rate clock.
Timer/PWM Module (S08TPMV3) R 7 6 5 4 3 2 1 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 W Reset Any write to TPMxCNTH clears the 16-bit counter 0 0 0 0 0 0 Figure 16-8. TPM Counter Register High (TPMxCNTH) R 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 W Reset Any write to TPMxCNTL clears the 16-bit counter 0 0 0 0 0 0 Figure 16-9.
Timer/PWM Module (S08TPMV3) 7 6 5 4 3 2 1 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 R W Reset Figure 16-10. TPM Counter Modulo Register High (TPMxMODH) 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 16-11. TPM Counter Modulo Register Low (TPMxMODL) Reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first counter overflow will occur. 16.3.
Timer/PWM Module (S08TPMV3) Table 16-5. TPMxCnSC Field Descriptions Field Description 7 CHnF Channel n flag. When channel n is an input-capture channel, this read/write bit is set when an active edge occurs on the channel n pin. When channel n is an output compare or edge-aligned/center-aligned PWM channel, CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers.
Timer/PWM Module (S08TPMV3) Table 16-6. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA X XX 00 Pin not used for TPM - revert to general purpose I/O or other peripheral control 0 00 01 Input capture 01 11 Capture on rising or falling edge Output compare Clear output on compare 11 Set output on compare Edge-aligned PWM High-true pulses (clear output on compare) Low-true pulses (set output on compare) 10 Center-aligned PWM X1 16.3.
Timer/PWM Module (S08TPMV3) In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes into a buffer where they remain latched until the other half is read. This latching mechanism also resets (becomes unlatched) when the TPMxCnSC register is written (whether BDM mode is active or not). Any write to the channel registers will be ignored during the input capture mode.
Timer/PWM Module (S08TPMV3) and influences the way the main counter operates. (In CPWM mode, the counter changes to an up/down mode rather than the up-counting mode used for general purpose timer functions.) The following sections describe the main counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM).
Timer/PWM Module (S08TPMV3) When the external clock source shares the TPM channel pin, this pin should not be used for other channel timing functions. For example, it would be ambiguous to configure channel 0 for input capture when the TPM channel 0 pin was also being used as the timer external clock source. (It is the user’s responsibility to avoid such settings.) The TPM channel could still be used in output compare mode for software timing functions (pin controls set not to affect the TPM channel pin).
Timer/PWM Module (S08TPMV3) 16.4.2.1 Input Capture Mode With the input-capture function, the TPM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input-capture channel, the TPM latches the contents of the TPM counter into the channel-value registers (TPMxCnVH:TPMxCnVL). Rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. In input capture mode, the TPMxCnVH and TPMxCnVL registers are read only.
Timer/PWM Module (S08TPMV3) OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH TPMxCHn OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 16-15. PWM Period and Pulse Width (ELSnA=0) When the channel value register is set to 0x0000, the duty cycle is 0%. 100% duty cycle can be achieved by setting the timer-channel register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting. This implies that the modulus setting must be less than 0xFFFF in order to get 100% duty cycle.
Timer/PWM Module (S08TPMV3) The output compare value in the TPM channel registers (times 2) determines the pulse width (duty cycle) of the CPWM signal (Figure 16-16). If ELSnA=0, a compare occurred while counting up forces the CPWM output signal low and a compare occurred while counting down forces the output high. The counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then counts down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL.
Timer/PWM Module (S08TPMV3) 16.5 16.5.1 Reset Overview General The TPM is reset whenever any MCU reset occurs. 16.5.2 Description of Reset Operation Reset clears the TPMxSC register which disables clocks to the TPM and disables timer overflow interrupts (TOIE=0).
Timer/PWM Module (S08TPMV3) to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will generate whenever the associated interrupt flag equals one. The user’s software must perform a sequence of steps to clear the interrupt flag before returning from the interrupt-service routine. TPM interrupt flags are cleared by a two-step process including a read of the flag bit while it is set (1) followed by a write of zero (0) to the bit.
Timer/PWM Module (S08TPMV3) 16.6.2.2.3 PWM End-of-Duty-Cycle Events For channels configured for PWM operation there are two possibilities. When the channel is configured for edge-aligned PWM, the channel flag gets set when the timer counter matches the channel value register which marks the end of the active duty cycle period. When the channel is configured for center-aligned PWM, the timer count matches the channel value register twice during each PWM cycle.
Chapter 17 Universal Serial Bus Device Controller (S08USBV1) 17.1 Introduction This chapter describes an universal serial bus device controller (S08USBV1) module that is based on the Universal Serial Bus Specification Rev 2.0. The USB bus is designed to replace existing bus interfaces such as RS-232, PS/2, and IEEE 1284 for PC peripherals.
Chapter 17 Universal Serial Bus Device Controller (S08USBV1) Table 17-1. USBVREN Configuration USBVREN 3.3-V Regulator VDD Supply Voltage Range 0 External 3.3-V Regulator (as input to VUSB33 pin) VUSB33 ≤ VDD Supply Voltage 1 Internal 3.3-V Regulator (no external supply connected to VUSB33 pin) 3.9 V ≤ VDD Supply Voltage ≤ 5.5V MC9S08JM60 Series Data Sheet, Rev.
Chapter 17 Universal Serial Bus Device Controller (S08USBV1) USBDP USBDN HCS08 CORE PORT A On Chip ICE AND DEBUG MODULE (DBG) USB SIE CPU USB ENDPOINT RAM RESET IRQ/TPMCLK HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT USB TRANSCEIVER 8-/16-BIT SERIAL PERIPHERAL INTERFACE MODULE (SPI2) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) COP IRQ LVD IIC MODULE (IIC) VDDAD USER Flash (IN BYTES) MC9S08JM60 = 60,912 MC9S08JM32 = 32,768 SS2 SPSCK2 MOSI2 MISO2 RxD2 TxD2 S
Universal Serial Bus Device Controller (S08USBV1) 17.1.4 Features Features of the USB module include: • USB 2.
Universal Serial Bus Device Controller (S08USBV1) Table 17-2. Operating Modes (continued) Mode Description Stop3 The USB module is optionally available in stop3. A reduced current consumption mode may be required for USB suspend mode per USB Specification Rev. 2.0, and stop3 mode is useful for achieving lower current consumption for the MCU and hence the overall USB device.
Universal Serial Bus Device Controller (S08USBV1) 17.2 External Signal Description The USB module requires both data and power pins. Table 17-3 describes each of the USB external pin Table 17-3. USB External Pins Name Port Direction Positive USB differential signal USBDP I/O Differential USB signaling. High impedance Negative USB differential signal USBDN I/O Differential USB signaling. High impedance USB voltage regulator power pin VUSB33 Power 17.2.1 Function Reset State 3.
Universal Serial Bus Device Controller (S08USBV1) 17.3.1 USB Control Register 0 (USBCTL0) 7 R 6 5 USBPU 0 0 W USBRESET Reset 0 4 3 USBRES MEN LPRESF 0 0 0 2 1 0 0 USBVREN 0 0 USBPHYEN 0 0 = Unimplemented or Reserved Figure 17-3. USB Transceiver and Regulator Control Register 0 (USBCTL0) Table 17-4. USBCTL0 Field Descriptions Field Description 7 USBRESET USB Reset — This bit generates a hard reset of the USB module, USBPHYEN and USBVREGEN bits will also be cleared.
Universal Serial Bus Device Controller (S08USBV1) R 7 6 5 4 3 2 1 0 0 0 ID5 ID4 ID3 ID2 ID1 ID0 0 0 0 0 0 1 0 0 W Reset = Unimplemented or Reserved Figure 17-4. Peripheral ID Register (PERID) Table 17-5. PERID Field Descriptions Field 5:0 ID[5:0] 17.3.3 Description Peripheral Configuration Number —This number is set to 0x04 and indicates that the peripheral is the full-speed USB module.
Universal Serial Bus Device Controller (S08USBV1) Table 17-7. REV Field Descriptions Field 8–0 REV[7:0] 17.3.5 Description Revision — Revision number of the USB module. Interrupt Status Register (INTSTAT) The INTSTAT contains bits for each of the interrupt source within the USB module. Each of these bits is qualified with its respective interrupt enable bits (see the interrupt enable register).
Universal Serial Bus Device Controller (S08USBV1) Table 17-9. INTSTAT Field Descriptions (continued) Field Description 1 ERRORF Error Flag — This bit is set when any of the error conditions within the ERRSTAT register has occurred. The firmware must then read the ERRSTAT register to determine the source of the error.
Universal Serial Bus Device Controller (S08USBV1) Table 17-10. INTENB Field Descriptions (continued) Field Description 1 ERROR ERROR Interrupt Enable — Setting this bit will enable ERROR interrupts. 0 Interrupt disabled 1 Interrupt enabled 0 USBRST USBRST Interrupt Enable — Setting this bit will enable USBRST interrupts. 0 Interrupt disabled 1 Interrupt enabled 17.3.7 Error Interrupt Status Register (ERRSTAT) The ERRSTAT contains bits for each of the error sources within the USB module.
Universal Serial Bus Device Controller (S08USBV1) Table 17-11. ERRSTAT Field Descriptions (continued) Field Description 3 DFN8F Data Field Error Flag — The data field received was not an interval of 8 bits. The USB Specification specifies that the data field must be an integer number of bytes. If the data field was not an integer number of bytes, this bit will be set.
Universal Serial Bus Device Controller (S08USBV1) Table 17-12. ERRSTAT Field Descriptions (continued) Field 1 CRC5 0 PIDERR 17.3.9 Description CRC5 Interrupt Enable — Setting this bit will enable CRC5 interrupts. 0 Interrupt disabled 1 Interrupt enabled PIDERR Interrupt Enable — Setting this bit will enable PIDERR interrupts. 0 Interrupt disabled 1 Interrupt enabled Status Register (STAT) The STAT reports the transaction status within the USB module.
Universal Serial Bus Device Controller (S08USBV1) Table 17-13. STAT Field Descriptions (continued) Field 3 IN 2 ODD Description In/Out Transaction — This bit indicates whether the last BDT updated was for a transmit (IN) transfer or a receive (OUT) data transfer.
Universal Serial Bus Device Controller (S08USBV1) 17.3.11 Address Register (ADDR) The ADDR register contains the unique 7-bit address the device will be recognized as through USB. The register is reset to 0x00 after the reset input has gone active or the USB module has decoded USB reset signaling. That will initialize the address register to decode address 0x00 as required by the USB specification. Firmware will change the value when it processes a SET_ADDRESS request.
Universal Serial Bus Device Controller (S08USBV1) R 7 6 5 4 3 2 1 0 0 0 0 0 0 FRM10 FRM9 FRM8 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-16. Frame Number Register High (FRMNUMH) Table 17-17. FRMNUMH Field Descriptions Field 2–0 FRM[10:8] Description Frame Number — These bits represent the high order bits of the 11-bit frame number. 17.3.
Universal Serial Bus Device Controller (S08USBV1) Table 17-18. EPCTLn Field Descriptions (continued) Field Description 1 EPSTALL Endpoint Stall — When set, this bit indicates that the endpoint is stalled. This bit has priority over all other control bits in the endpoint control register, but is only valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint will cause the USB module to return a STALL handshake. Once an endpoint is stalled it requires intervention from the host controller.
Universal Serial Bus Device Controller (S08USBV1) internal basic virtual component interface (BVCI) compliant target and initiator buses. The BVCI target interface is used to configure the USB SIE and to provide status and interrupts to CPU. The BVCI initiator interface provides the integrated DMA controller access to the buffer descriptor table (BDT), and transfers USB data to or from USB RAM memory. 17.4.1.1.
Universal Serial Bus Device Controller (S08USBV1) • Bit stuffing violation If a properly formatted packet is received, the receiver logic initiates a handshake response to the host. If the packet is not decoded correctly due to bit stuff violation, CRC error or other packet level problem, the receiver ignores it. The USB host will eventually time-out waiting for a response, and retransmit the packet.
Universal Serial Bus Device Controller (S08USBV1) 17.4.1.5 USB On-Chip Voltage Regulator (VREG) The on-chip 3.3-V regulator provides a stable power source to power the USB internal transceiver and provide for the termination of an internal or external pullup resistor. When the on-chip regulator is enabled, it requires a voltage supply input in the range from 3.9 V to 5.5 V, and the voltage regulator output will be in the range of 3.0 V to 3.6 V. With a dedicated on-chip USB 3.
Universal Serial Bus Device Controller (S08USBV1) USB DEVICE 3.3 V VUSB33 RDPPU USBDP USBDN Figure 17-18. USBDP/USBDN Pullup Resistor Configuration for USB module 17.4.1.7 USB Powering and USBDP Pullup Enable Options The USB module provides a single-chip solution for USB device applications that are self-powered or bus-powered. The USB device needs to know when it has a valid USB connection in order to enable or disable the pullup resistor on the USBDP line.
Universal Serial Bus Device Controller (S08USBV1) 17.4.2 Buffer Descriptor Table (BDT) To efficiently manage USB endpoint communications, the USB module implements a buffer descriptor table (BDT) comprised of buffer descriptors (BD) in the local USB RAM. The BD entries provide status or control information for a corresponding endpoint. The BD entries also provide an address to the endpoint’s buffer. A single BD for an endpoint direction requires 3-bytes.
Universal Serial Bus Device Controller (S08USBV1) Table 17-21. USB RAM Organization USB RAM Offset USB RAM Description of Contents 0x00 Endpoint 0 IN Endpoint 0, OUT Endpoint 1 Endpoint 2 BDT Endpoint 3 Endpoint 4 Endpoint 5, Buffer EVEN Endpoint 5, Buffer ODD Endpoint 6, Buffer EVEN 0x1D Endpoint 6, Buffer ODD 0x1E RESERVED 0x1F RESERVED 0x20 USB RAM available for endpoint buffers 0xFF When the USB module receives a USB token on an enabled endpoint, it interrogates the BDT.
Universal Serial Bus Device Controller (S08USBV1) • • How much data was transmitted or received. Where the buffer resides in buffer memory The BDT is composed of buffer descriptors (BD) which are used to define and control the actual buffers in the USB RAM space. BDs always occur as a 3-bytes block. See Figure 17-19 for the BD example of Endpoint 0 IN start from USB RAM offset 0x00. The format for the buffer descriptor is shown in Table 17-22.
Universal Serial Bus Device Controller (S08USBV1) Table 17-22. Buffer Descriptor Table Fields (continued) Field BC[7:0] EPADR[9:4] 17.4.3 Description Byte Count — The Byte Count bits represent the 8-bit byte count. The USB module serial interface engine (SIE) will change this field upon the completion of a RX transfer with the byte count of the data received. Note that while USB supports packets as large as 1023 bytes for isochronous endpoints, this module limits packet size to 64 bytes.
Universal Serial Bus Device Controller (S08USBV1) = USB Host USB RST = Function SOF USBRST Interrupt Generated SETUP TOKEN SOF Interrupt Generated DATA ACK TOKDNE Interrupt Generated IN TOKEN DATA ACK TOKDNE Interrupt Generated OUT TOKEN DATA ACK TOKDNE Interrupt Generated Figure 17-20. USB Packet Flow The USB has two sources of data overrun error: • The memory latency to the local USB RAM interface may be too high and cause the receive buffer to overflow.
Universal Serial Bus Device Controller (S08USBV1) appropriate course of action for future transactions — stalling the endpoint, canceling the transfer, disabling the endpoint, etc. 17.4.4 USB Packet Processing Packet processing for a USB device consists of managing buffers for IN (to the USB Host) and OUT (to the USB device) transactions. Packet processing is further divided into request processing on Endpoint 0, and data packet processing on the data endpoints. 17.4.4.
Universal Serial Bus Device Controller (S08USBV1) 2. Create BDT entries for Endpoint 0 OUT, and set the DTS and OWN bits to 1. 3. Wait for interrupt TOKDNE. 4. Read STAT register. — The status register must show Endpoint 0, RX. If it does not, then assert the EPSTALL bit in the endpoint control register. 5. Read Endpoint 0 OUT BD. — Verify that the token type is a SETUP token. If it is not, then assert the EPSTALL bit in the endpoint control register. 6. Decode and process the setup packet.
Universal Serial Bus Device Controller (S08USBV1) 17.4.6 Suspend/Resume The USB supports a single low-power mode called suspend. Getting into and out of the suspend state is described in the following sections. 17.4.6.1 Suspend The USB host can put a single device or the entire bus into the suspend state at any time. The MCU supports suspend mode for low power. Suspend mode will be entered when the USB data lines are in the idle state for more than 3 ms.
Universal Serial Bus Device Controller (S08USBV1) a resume from low-power suspend. This will trigger an asynchronous interrupt to wake the CPU from stop3 mode and resume clocks to the USB module. NOTE As a precaution, after LPRESF is set, firmware must check the state of the USB bus to see if the K-state was a result of a transient event and not a true host-initiated resume. If this is the case, then the device can drop back into stop3 if necessary.
Universal Serial Bus Device Controller (S08USBV1) • • • • USB transceiver disabled USBDP pullup disabled Endpoints disabled USB address register set to zero 17.4.8 Interrupts Interrupts from the INTSTAT register signify events which occur during normal operation — USB start of frame tokens (TOKSOF), packet completion (TOKDNE), USB bus reset (USBRST), endpoint errors (ERROR), suspend and resume (SLEEP and RESUME), and endpoint stalled (STALL).
Universal Serial Bus Device Controller (S08USBV1) MC9S08JM60 Series Data Sheet, Rev.
Chapter 18 Development Support 18.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip flash and other nonvolatile memories.
Development Support 18.1.
Development Support • Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller. Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system.
Development Support When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU into active background mode after reset. The specific conditions for forcing active background depend upon the HCS08 derivative (refer to the introduction to this Development Support section).
Development Support Figure 18-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges.
Development Support Figure 18-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles).
Development Support Figure 18-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it.
Development Support 18.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commands and data are sent MSB-first using a custom BDC communications protocol. Active background mode commands require that the target MCU is currently in the active background mode while non-intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program.
Development Support Table 18-1. BDC Command Summary Command Mnemonic 1 Active BDM/ Non-intrusive Coding Structure Description SYNC Non-intrusive n/a1 Request a timed reference pulse to determine target BDC communication speed ACK_ENABLE Non-intrusive D5/d Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. ACK_DISABLE Non-intrusive D6/d Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D.
Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: • Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.
Development Support 18.3 On-Chip Debug System (DBG) Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture.
Development Support the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry in the FIFO. In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information is available at the FIFO data port.
Development Support A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. The tag vs. force terminology is used in two contexts within the debug module. The first context refers to breakpoint requests from the debug module to the CPU.
Development Support A-Only — Trigger when the address matches the value in comparator A A OR B — Trigger when the address matches either the value in comparator A or the value in comparator B A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match.
Development Support 18.3.6 Hardware Breakpoints The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions described in Section 18.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue.
Development Support 18.4.1.1 BDC Status and Control Register (BDCSCR) This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 R 6 5 4 3 BKPTEN FTS CLKSW BDMACT ENBDM 2 1 0 WS WSF DVF W Normal Reset 0 0 0 0 0 0 0 0 Reset in Active BDM: 1 1 0 0 1 0 0 0 = Unimplemented or Reserved Figure 18-5.
Development Support Table 18-2. BDCSCR Register Field Descriptions (continued) Field Description 2 WS Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work.
Development Support Table 18-3. SBDFR Register Field Description Field Description 0 BDFR Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. 18.4.3 DBG Registers and Control Bits The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control and status registers.
Development Support 18.4.3.6 Debug FIFO Low Register (DBGFL) This register provides read-only access to the low-order eight bits of the FIFO. Writes to this register have no meaning or effect. Reading DBGFL causes the FIFO to shift to the next available word of information. When the debug module is operating in event-only modes, only 8-bit data is stored into the FIFO (high-order half of each FIFO word is unused).
Development Support 18.4.3.7 Debug Control Register (DBGC) This register can be read or written at any time. 7 6 5 4 3 2 1 0 DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN 0 0 0 0 0 0 0 0 R W Reset Figure 18-7. Debug Control Register (DBGC) Table 18-4. DBGC Register Field Descriptions Field Description 7 DBGEN Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
Development Support 18.4.3.8 Debug Trigger Register (DBGT) This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired to 0s. 7 6 TRGSEL BEGIN 0 0 R 5 4 0 0 3 2 1 0 TRG3 TRG2 TRG1 TRG0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 18-8. Debug Trigger Register (DBGT) Table 18-5.
Development Support 18.4.3.9 Debug Status Register (DBGS) This is a read-only status register. R 7 6 5 4 3 2 1 0 AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 18-9. Debug Status Register (DBGS) Table 18-6. DBGS Register Field Descriptions Field Description 7 AF Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A condition was met since arming.
Appendix A Electrical Characteristics A.1 Introduction This appendix contains electrical and timing specifications for the MC9S08JM60 series of microcontrollers available at the time of publication. A.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table A-1.
Appendix A Electrical Characteristics Table A-2. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD – 0.3 to + 5.8 V Input voltage VIn – 0.3 to VDD + 0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 ID ± 25 mA IDD 120 mA Tstg –55 to +150 °C Maximum current into VDD Storage temperature 1 Input must be current limited to the value specified.
Appendix A Electrical Characteristics The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Eqn. A-1 where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O << Pint and can be neglected.
Appendix A Electrical Characteristics Table A-4. ESD and Latch-up Test Conditions Model Human Body Description Symbol Value Unit Series Resistance R1 1500 Ω Storage Capacitance C 100 pF Number of Pulse per pin — 3 Minimum input voltage limit –2.5 V Maximum input voltage limit 7.5 V Latch-up Table A-5. ESD and Latch-Up Protection Characteristics Num A.
Appendix A Electrical Characteristics Table A-6. DC Characteristics (continued) Num C 5 6 Parameter P Output low current — Max. total IOL for all ports 5V 3V Symbol Min Typical1 Max. Unit IOLT — — — — 100 60 mA VIH 0.65 × VDD 0.70 × VDD — — — 0.35 × VDD C Input high voltage; all digital inputs 5V 3V V 7 C Input low voltage; all digital inputs VIL — 8 C Input hysteresis; all digital inputs Vhys 0.06 × VDD 9 C Input leakage current (per pin); input only pins |IIn| — 0.
Appendix A Electrical Characteristics Table A-6. DC Characteristics (continued) Num C 19 20 21 22 23 P P P C P 24 C 25 T 26 P Parameter Min Typical1 Max. 3.9 4.0 4.0 4.1 4.1 4.2 2.48 2.54 2.56 2.62 2.64 2.70 4.5 4.6 4.6 4.7 4.7 4.8 4.2 4.3 4.3 4.4 4.4 4.5 2.84 2.90 2.92 2.98 3.00 3.06 2.66 2.72 2.74 2.80 2.82 2.88 Vhys — — 100 60 — — mV mV VBG 1.19 1.20 1.
Appendix A Electrical Characteristics Typical VOL vs. IOL AT VDD = 5V 0.7 0.6 Hot (85°C) 1.4 Room (25°C) 1.2 Room (25°C) 1.0 Cold (-40°C) Cold (-40°C) VOL (v) 0.5 VOL (v) Typical V OL vs. IOL AT V DD = 3V 0.4 0.3 Hot (85°C) 0.8 0.6 0.2 0.4 0.1 0.2 0.0 0.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.0 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IOL (mA) IOL (mA) Figure A-1. Typical Low-side Drive (sink) characteristics – High Drive (PTxDSn = 1) T ypical V O L v s.
Appendix A Electrical Characteristics Typical VDD - VOH vs. IOH AT VDD = 3V Typical VDD - VOH vs. IOH AT VDD= 5V 1.2 Hot (85°C) 1.0 Room(25°C) 0.8 VDD - VOH (v) VDD - VOH (v) 1.2 Cold (-40°C) 0.6 0.4 0.2 Hot (85°C) 1.0 Room (25°C) 0.8 Cold (-40°C) 0.6 0.4 0.2 0.0 0.0 0 -1 -2 -3 -4 -5 0 IOH(mA) -1 IOH (mA) -2 -3 Figure A-4. Typical High-side Drive (source) characteristics – Low Drive (PTxDSn = 0) MC9S08JM60 Series Data Sheet, Rev.
Appendix A Electrical Characteristics A.7 Supply Current Characteristics Table A-7. Supply Current Characteristics VDD (V) Typical1 Max2 5 1.1 1.6 3 0.8 1.5 5 4.9 8 3 4.3 7 5 23 30 3 22 30 5 0.80 –40 °C 25 °C 85 °C 3 0.80 –40 °C 25 °C 85 °C 5 0.90 3 0.
Appendix A Electrical Characteristics 6 Here USB module is enabled and clocked at 48 MHz (USBEN = 1, USBVREN =1, USBPHYEN = 1 and USBPU = 1), and D+ and D– pull down by two 15.1kΩ resisters independently. The current consumption may be much higher when the packets are being transmitted through the attached cable. 7 MCU enters into Stop3 mode, USB bus in idle state. The USB suspend current will be dominated by the D+ pull up resister. A.8 Analog Comparator (ACMP) Electricals Table A-8.
Appendix A Electrical Characteristics Table A-9. 5 Volt 12-bit ADC Operating Conditions (continued) Characteristic ADC Conversion Clock Freq. Conditions Symb High Speed (ADLPC=0) fADCK Low Power (ADLPC=1) Min Typ1 Max 0.4 — 8.0 0.4 — 4.0 Unit Comment MHz 1 Typical values assume VDDAD = 5.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference.
Appendix A Electrical Characteristics Table A-10. 5 Volt 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) C Symb Min Typ1 Max Unit Supply Current ADLPC=1 ADLSMP=1 ADCO=1 T IDDAD — 133 — μA Supply Current ADLPC=1 ADLSMP=0 ADCO=1 T IDDAD — 218 — μA Supply Current ADLPC=0 ADLSMP=1 ADCO=1 T IDDAD — 327 — μA Supply Current ADLPC=0 ADLSMP=0 ADCO=1 T IDDAD — 0.582 1 mA IDDAD — 0.011 1 μA 2 3.3 5 1.25 2 3.3 — 20 — — 40 — — 3.5 — — 23.5 — — ±3.
Appendix A Electrical Characteristics Table A-10. 5 Volt 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued) Min Typ1 Max — ±1 ±4.0 — ±0.5 ±1 — ±0.5 ±0.5 — –1 to 0 –1 to 0 — — ±0.5 8 bit mode — — ±0.5 12 bit mode — ±1 ±10 — ±0.2 ±2.5 — ±0.1 ±1 — 1.396 — — 3.266 — — 3.
Appendix A Electrical Characteristics A.10 External Oscillator (XOSC) Characteristics Table A-11.
Appendix A Electrical Characteristics A.11 MCG Specifications Table A-12. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient) Num C Rating Symbol Min Typical Max Unit 1 Internal reference frequency - factory trimmed at VDD = P 5 V and temperature = 25 °C fint_ft — 31.25 — kHz 2 P Average internal reference frequency – untrimmed 1 fint_ut 25 32.7 41.66 kHz P Average internal reference frequency Q – user trimmed fint_t 31.25 — 39.
Appendix A Electrical Characteristics 4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. 5 Jitter measurements are based upon a 48 MHz MCGOUT clock frequency..
Appendix A Electrical Characteristics textrst RESET PIN Figure A-6. Reset Timing tIHIL IRQ/KBIPx IRQ/KBIPx tILIH Figure A-7. IRQ/KBIPx Timing A.12.2 Timer/PWM (TPM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table A-14.
Appendix A Electrical Characteristics tICPW TPMxCHn TPMxCHn tICPW Figure A-9. Timer Input Capture Pulse A.12.3 SPI Characteristics Table A-15 and Figure A-10 through Figure A-13 describe the timing requirements for the SPI system. Table A-15.
Appendix A Electrical Characteristics 1 Refer to Figure A-10 through Figure A-13. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. 3 Time to data active from high-impedance state. 4 Hold time to high-impedance state. 2 SS1 (OUTPUT) 5 4 SCK (CPOL = 1) (OUTPUT) 5 4 6 MISO (INPUT) 7 MSB IN2 10 MOSI (OUTPUT) 3 1 2 SCK (CPOL = 0) (OUTPUT) BIT 6 . . .
Appendix A Electrical Characteristics SS(1) (OUTPUT) 1 3 2 SCK (CPOL = 0) (OUTPUT) 5 4 SCK (CPOL = 1) (OUTPUT) 5 4 6 MISO (INPUT) 7 MSB IN(2) BIT 6 . . . 1 LSB IN 11 10 MOSI (OUTPUT) MSB OUT(2) BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-11.
Appendix A Electrical Characteristics SS (INPUT) 3 1 2 SCK (CPOL = 0) (INPUT) 5 4 SCK (CPOL = 1) (INPUT) 5 4 10 MISO (OUTPUT) SEE NOTE SLAVE 11 MSB OUT 6 8 MOSI (INPUT) 9 BIT 6 . . . 1 SLAVE LSB OUT 7 MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received Figure A-13. SPI Slave Timing (CPHA = 1) A.13 Flash Specifications This section provides details about program/erase times and program-erase endurance for the flash memory.
Appendix A Electrical Characteristics 2 The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 4 Typical endurance for Flash is based on the intrinsic bitcell performance.
Appendix A Electrical Characteristics Table A-18. Radiated Emissions Parameter Radiated emissions, electric field 1 Symbol VRE_TEM Conditions VDD = 5.0 V TA = +25oC Frequency fOSC/fBUS Level1 (Max) 0.15 – 50 MHz 20 50 – 150 MHz 27 150 – 500 MHz 27 500 – 1000 MHz 4 MHz crystal 24 MHz Bus Unit dBμV 16 IEC Level 1 — SAE Level 3 — Data based on qualification test results. MC9S08JM60 Series Data Sheet, Rev.
Appendix A Electrical Characteristics MC9S08JM60 Series Data Sheet, Rev.
Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information This section contains ordering numbers for MC9S08JM60 series devices. See below for an example of the device numbering system. Table B-1. Device Numbering System Device 1 2 B.2 Available Packages2 Memory Number1 Flash RAM Type MC9S08JM60 60,912 4096 MC9S08JM32 32,768 2048 64-pin LQFP 64-pin QFP 48-pin QFN 44-pin LQFP See Table 1-1 for a complete description of modules included on each device.
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