Datasheet

Chapter 3 Modes of Operation
MC9S08JM60 Series Data Sheet, Rev. 3
Freescale Semiconductor 37
3.6 Stop Modes
One of two stop modes is entered upon execution of a STOP instruction when STOPE in SOPT1 is set. In
any stop mode, the bus and CPU clocks are halted. The MCG module can be configured to leave the
reference clocks running. See Chapter 12, “Multi-Purpose Clock Generator (S08MCGV1),” for more
information.
Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various
conditions. The selected mode is entered following the execution of a STOP instruction.
3.6.1 Stop3 Mode
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time
clock (RTC) interrupt, the USB resume interrupt, LVD, ADC, IRQ, KBI, SCI, or the ACMP.
If stop3 is exited by means of the RESET
pin, then the MCU is reset and operation will resume after taking
the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the
appropriate interrupt vector.
3.6.1.1 LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. If the
user attempts to enter stop2 with the LVD enabled for stop, the MCU will enter stop3 instead.
For the ADC to operate, the LVD must be left enabled when entering stop3. For the ACMP to operate when
ACGBS in ACMPSC is set, the LVD must be left enabled when entering stop3.
For the XOSC to operate with an external reference when RANGE in MCGC2 is set, the LVD must be left
enabled when entering stop3.
Table 3-1. Stop Mode Selection
STOPE ENBDM
1
1
ENBDM is located in the BDCSCR which is only accessible through BDC commands, see Section 18.4.1.1,
“BDC Status and Control Register (BDCSCR).”
LVD E LVD SE PP DC St op Mo de
0 x x x Stop modes disabled; illegal opcode reset if STOP
instruction executed
1 1 x x Stop3 with BDM enabled
2
2
When in stop3 mode with BDM enabled, The S
IDD
will be near R
IDD
levels because internal clocks are
enabled.
1 0 Both bits must be 1 x Stop3 with voltage regulator active
1 0 Either bit a 0 0 Stop3
1 0 Either bit a 0 1 Stop2