Datasheet

Electrical Characteristics
MC9S08FL16 Series Data Sheet, Rev. 3
Freescale Semiconductor 11
T
J
= T
A
+ (P
D
 
JA
) Eqn. 1
where:
T
A
= Ambient temperature, C

JA
= Package thermal resistance, junction-to-ambient, C/W
P
D
= P
int
P
I/O
P
int
= I
DD
 V
DD
, Watts — chip internal power
P
I/O
= Power dissipation on input and output pins — user determined
For most applications, P
I/O
far much smaller than P
int
and can be neglected. An approximate relationship
between P
D
and T
J
(if P
I/O
is neglected) is:
P
D
= K  (T
J
+ 273 C) Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = P
D
 (T
A
+ 273 C) + 
JA
 (P
D
)
2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
P
D
(at equilibrium) for an known T
A
. Using this value of K, the values of P
D
and T
J
can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of T
A
.
5.5 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions must be taken to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
During the device qualification, ESD stresses were performed for the human body model (HBM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless instructed otherwise in the device
specification.
Table 5. ESD and Latch-Up Test Conditions
Model Description Symbol Value Unit
Human
body
Series resistance R1 1500 
Storage capacitance C 100 pF
Number of pulses per pin — 3 —
Latch-up
Minimum input voltage limit — –2.5 V
Maximum input voltage limit — 7.5 V