Datasheet

Chapter 1 Device Overview

MC9S08DV60 Series Data Sheet, Rev 3

Freescale Semiconductor 25

Figure 1-2. MC9S08DV60 System Clock Distribution Diagram

TPM1 TPM2 IIC SCI1 SCI2

BDC

CPU

ADC

MSCAN FLASH

MCG

MCGOUT

÷2

BUSCLK

MCGLCLK

MCGERCLK

COP

* The ﬁxed frequency clock (FFCLK) is internally

synchronized to the bus clock and must not exceed one half

of the bus clock frequency.

Flash has frequency

requirements for program

and erase operation. See

the electricals appendix

for details.

ADC has min and max

frequency requirements.

See the ADC chapter

and electricals appendix

for details.

XOSC

EXTAL XTAL

SPI

FFCLK*

MCGFFCLK

RTC

1 kHZ

LPO

TPM1CLK TPM2CLK

MCGIRCLK

÷2