Datasheet
Table Of Contents
- Chapter 1 Device Overview
- Chapter 2 Pins and Connections
- Chapter 3 Modes of Operation
- Chapter 4 Memory
- 4.1 MC9S08DN60 Series Memory Map
- 4.2 Reset and Interrupt Vector Assignments
- 4.3 Register Addresses and Bit Assignments
- 4.4 RAM
- 4.5 Flash and EEPROM
- 4.5.1 Features
- 4.5.2 Program and Erase Times
- 4.5.3 Program and Erase Command Execution
- 4.5.4 Burst Program Execution
- 4.5.5 Sector Erase Abort
- 4.5.6 Access Errors
- 4.5.7 Block Protection
- 4.5.8 Vector Redirection
- 4.5.9 Security
- 4.5.10 EEPROM Mapping
- 4.5.11 Flash and EEPROM Registers and Control Bits
- 4.5.11.1 Flash and EEPROM Clock Divider Register (FCDIV)
- 4.5.11.2 Flash and EEPROM Options Register (FOPT and NVOPT)
- 4.5.11.3 Flash and EEPROM Configuration Register (FCNFG)
- 4.5.11.4 Flash and EEPROM Protection Register (FPROT and NVPROT)
- 4.5.11.5 Flash and EEPROM Status Register (FSTAT)
- 4.5.11.6 Flash and EEPROM Command Register (FCMD)
- Chapter 5 Resets, Interrupts, and General System Control
- 5.1 Introduction
- 5.2 Features
- 5.3 MCU Reset
- 5.4 Computer Operating Properly (COP) Watchdog
- 5.5 Interrupts
- 5.6 Low-Voltage Detect (LVD) System
- 5.7 MCLK Output
- 5.8 Reset, Interrupt, and System Control Registers and Control Bits
- 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC)
- 5.8.2 System Reset Status Register (SRS)
- 5.8.3 System Background Debug Force Reset Register (SBDFR)
- 5.8.4 System Options Register 1 (SOPT1)
- 5.8.5 System Options Register 2 (SOPT2)
- 5.8.6 System Device Identification Register (SDIDH, SDIDL)
- 5.8.7 System Power Management Status and Control 1 Register (SPMSC1)
- 5.8.8 System Power Management Status and Control 2 Register (SPMSC2)
- Chapter 6 Parallel Input/Output Control
- 6.1 Port Data and Data Direction
- 6.2 Pull-up, Slew Rate, and Drive Strength
- 6.3 Pin Interrupts
- 6.4 Pin Behavior in Stop Modes
- 6.5 Parallel I/O and Pin Control Registers
- 6.5.1 Port A Registers
- 6.5.1.1 Port A Data Register (PTAD)
- 6.5.1.2 Port A Data Direction Register (PTADD)
- 6.5.1.3 Port A Pull Enable Register (PTAPE)
- 6.5.1.4 Port A Slew Rate Enable Register (PTASE)
- 6.5.1.5 Port A Drive Strength Selection Register (PTADS)
- 6.5.1.6 Port A Interrupt Status and Control Register (PTASC)
- 6.5.1.7 Port A Interrupt Pin Select Register (PTAPS)
- 6.5.1.8 Port A Interrupt Edge Select Register (PTAES)
- 6.5.2 Port B Registers
- 6.5.2.1 Port B Data Register (PTBD)
- 6.5.2.2 Port B Data Direction Register (PTBDD)
- 6.5.2.3 Port B Pull Enable Register (PTBPE)
- 6.5.2.4 Port B Slew Rate Enable Register (PTBSE)
- 6.5.2.5 Port B Drive Strength Selection Register (PTBDS)
- 6.5.2.6 Port B Interrupt Status and Control Register (PTBSC)
- 6.5.2.7 Port B Interrupt Pin Select Register (PTBPS)
- 6.5.2.8 Port B Interrupt Edge Select Register (PTBES)
- 6.5.3 Port C Registers
- 6.5.4 Port D Registers
- 6.5.4.1 Port D Data Register (PTDD)
- 6.5.4.2 Port D Data Direction Register (PTDDD)
- 6.5.4.3 Port D Pull Enable Register (PTDPE)
- 6.5.4.4 Port D Slew Rate Enable Register (PTDSE)
- 6.5.4.5 Port D Drive Strength Selection Register (PTDDS)
- 6.5.4.6 Port D Interrupt Status and Control Register (PTDSC)
- 6.5.4.7 Port D Interrupt Pin Select Register (PTDPS)
- 6.5.4.8 Port D Interrupt Edge Select Register (PTDES)
- 6.5.5 Port E Registers
- 6.5.6 Port F Registers
- 6.5.7 Port G Registers
- 6.5.1 Port A Registers
- Chapter 7 Central Processor Unit (S08CPUV3)
- 7.1 Introduction
- 7.2 Programmer’s Model and CPU Registers
- 7.3 Addressing Modes
- 7.4 Special Operations
- 7.5 HCS08 Instruction Set Summary
- Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
- 8.1 Introduction
- 8.2 External Signal Description
- 8.3 Register Definition
- 8.4 Functional Description
- 8.4.1 Operational Modes
- 8.4.1.1 FLL Engaged Internal (FEI)
- 8.4.1.2 FLL Engaged External (FEE)
- 8.4.1.3 FLL Bypassed Internal (FBI)
- 8.4.1.4 FLL Bypassed External (FBE)
- 8.4.1.5 PLL Engaged External (PEE)
- 8.4.1.6 PLL Bypassed External (PBE)
- 8.4.1.7 Bypassed Low Power Internal (BLPI)
- 8.4.1.8 Bypassed Low Power External (BLPE)
- 8.4.1.9 Stop
- 8.4.2 Mode Switching
- 8.4.3 Bus Frequency Divider
- 8.4.4 Low Power Bit Usage
- 8.4.5 Internal Reference Clock
- 8.4.6 External Reference Clock
- 8.4.7 Fixed Frequency Clock
- 8.4.1 Operational Modes
- 8.5 Initialization / Application Information
- 8.5.1 MCG Module Initialization Sequence
- 8.5.2 MCG Mode Switching
- 8.5.2.1 Example # 1: Moving from FEI to PEE Mode: External Crystal = 4 MHz, Bus Frequency = 8 MHz
- 8.5.2.2 Example # 2: Moving from PEE to BLPI Mode: External Crystal = 4 MHz, Bus Frequency =16 kHz
- 8.5.2.3 Example #3: Moving from BLPI to FEE Mode: External Crystal = 4 MHz, Bus Frequency = 16 MHz
- 8.5.2.4 Example # 4: Moving from FEI to PEE Mode: External Crystal = 8 MHz, Bus Frequency = 8 MHz
- 8.5.3 Calibrating the Internal Reference Clock (IRC)
- Chapter 9 Analog Comparator (S08ACMPV3)
- Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
- 10.1 Introduction
- 10.2 External Signal Description
- 10.3 Register Definition
- 10.3.1 Status and Control Register 1 (ADCSC1)
- 10.3.2 Status and Control Register 2 (ADCSC2)
- 10.3.3 Data Result High Register (ADCRH)
- 10.3.4 Data Result Low Register (ADCRL)
- 10.3.5 Compare Value High Register (ADCCVH)
- 10.3.6 Compare Value Low Register (ADCCVL)
- 10.3.7 Configuration Register (ADCCFG)
- 10.3.8 Pin Control 1 Register (APCTL1)
- 10.3.9 Pin Control 2 Register (APCTL2)
- 10.3.10 Pin Control 3 Register (APCTL3)
- 10.4 Functional Description
- 10.5 Initialization Information
- 10.6 Application Information
- Chapter 11 Inter-Integrated Circuit (S08IICV2)
- Chapter 12 Serial Peripheral Interface (S08SPIV3)
- Chapter 13 Serial Communications Interface (S08SCIV4)
- Chapter 14 Real-Time Counter (S08RTCV1)
- Chapter 15 Timer Pulse-Width Modulator (S08TPMV3)
- Chapter 16 Development Support
- 16.1 Introduction
- 16.2 Background Debug Controller (BDC)
- 16.3 On-Chip Debug System (DBG)
- 16.4 Register Definition
- 16.4.1 BDC Registers and Control Bits
- 16.4.2 System Background Debug Force Reset Register (SBDFR)
- 16.4.3 DBG Registers and Control Bits
- 16.4.3.1 Debug Comparator A High Register (DBGCAH)
- 16.4.3.2 Debug Comparator A Low Register (DBGCAL)
- 16.4.3.3 Debug Comparator B High Register (DBGCBH)
- 16.4.3.4 Debug Comparator B Low Register (DBGCBL)
- 16.4.3.5 Debug FIFO High Register (DBGFH)
- 16.4.3.6 Debug FIFO Low Register (DBGFL)
- 16.4.3.7 Debug Control Register (DBGC)
- 16.4.3.8 Debug Trigger Register (DBGT)
- 16.4.3.9 Debug Status Register (DBGS)
- Appendix A Electrical Characteristics
- A.1 Introduction
- A.2 Parameter Classification
- A.3 Absolute Maximum Ratings
- A.4 Thermal Characteristics
- A.5 ESD Protection and Latch-Up Immunity
- A.6 DC Characteristics
- A.7 Supply Current Characteristics
- A.8 Analog Comparator (ACMP) Electricals
- A.9 ADC Characteristics
- A.10 External Oscillator (XOSC) Characteristics
- A.11 MCG Specifications
- A.12 AC Characteristics
- A.13 Flash and EEPROM
- A.14 EMC Performance
- Appendix B Timer Pulse-Width Modulator (TPMV2)
- Appendix C Ordering Information and Mechanical Drawings

Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
82 Freescale Semiconductor
6.3.2 Edge and Level Sensitivity
A valid edge or level on an enabled port pin will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt
request will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in
PTxSC provided all enabled port inputs are at their deasserted levels. PTxIF will remain set if any enabled
port pin is asserted while attempting to clear by writing a 1 to PTxACK.
6.3.3 Pull-up/Pull-down Resistors
The port interrupt pins can be configured to use an internal pull-up/pull-down resistor using the associated
I/O port pull-up enable register. If an internal resistor is enabled, the PTxES register is used to select
whether the resistor is a pull-up (PTxESn = 0) or a pull-down (PTxESn = 1).
6.3.4 Pin Interrupt Initialization
When an interrupt pin is first enabled, it is possible to get a false interrupt flag. To prevent a false interrupt
request during pin interrupt initialization, the user should do the following:
1. Mask interrupts by clearing PTxIE in PTxSC.
2. Select the pin polarity by setting the appropriate PTxESn bits in PTxES.
3. If using internal pull-up/pull-down device, configure the associated pull enable bits in PTxPE.
4. Enable the interrupt pins by setting the appropriate PTxPSn bits in PTxPS.
5. Write to PTxACK in PTxSC to clear any false interrupts.
6. Set PTxIE in PTxSC to enable interrupts.
6.4 Pin Behavior in Stop Modes
Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An
explanation of pin behavior for the various stop modes follows:
• Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as
before the STOP instruction was executed. CPU register status and the state of I/O registers should
be saved in RAM before the STOP instruction is executed to place the MCU in stop2 mode. Upon
recovery from stop2 mode, before accessing any I/O, the user should examine the state of the PPDF
bit in the SPMSC2 register. If the PPDF bit is 0, I/O must be initialized as if a power on reset had
occurred. If the PPDF bit is 1, peripherals may require initialization to be restored to their pre-stop
condition. This can be done using data previously stored in RAM if it was saved before the STOP
instruction was executed. The user must then write a 1 to the PPDACK bit in the SPMSC2 register.
Access to I/O is now permitted again in the user application program.
• In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon
recovery, normal I/O function is available to the user.