Datasheet

Chapter 5 Resets, Interrupts, and General System Control
MC9S08DN60 Series Data Sheet, Rev 3
74 Freescale Semiconductor
5.8.4 System Options Register 1 (SOPT1)
This high page register is a write-once register so only the first write after reset is honored. It can be read
at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to
avoid accidental changes to these sensitive settings. This register should be written during the user’s reset
initialization program to set the desired controls even if the desired settings are the same as the reset
settings.
76543210
R
COPT STOPE Reserved IICPS
000
W
Reset: 11000000
= Unimplemented or Reserved
Figure 5-5. System Options Register 1 (SOPT1)
Table 5-5. SOPT1 Register Field Descriptions
Field Description
7:6
COPT[1:0]
COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with
COPCLKS in SOPT2 defines the COP timeout period. See Table 5-6.
5
STOPE
Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
3
IICPS
IIC Pin Select— This write-once bit selects the location of the SCL and SDA pins of the IIC module.
0 SCL on PTF2, SDA on PTF3.
1 SCL on PTE4, SDA on PTE5.
Table 5-6. COP Configuration Options
Control Bits
Clock Source
COP Window
1
Opens
(COPW = 1)
1
Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column
displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode
(COPW = 1).
COP Overflow Count
COPCLKS COPT[1:0]
N/A 0:0 N/A N/A COP is disabled
0 0:1
1 kHz N/A
2
5
cycles (32 ms
2
)
2
Values shown in milliseconds based on t
LPO
= 1 ms. See t
LPO
in the appendix Section A.12.1, “Control Timing,” for the
tolerance of this value.
0 1:0
1 kHz N/A
2
8
cycles (256 ms
1
)
0 1:1
1 kHz N/A
2
10
cycles (1.024 s
1
)
1 0:1
Bus 6144 cycles
2
13
cycles
1 1:0
Bus 49,152 cycles
2
16
cycles
1 1:1
Bus 196,608 cycles
2
18
cycles