Datasheet

Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 57
if PRDIV8 = 0 — f
FCLK
= f
Bus
÷ (DIV + 1) Eqn. 4-1
if PRDIV8 = 1 — f
FCLK
= f
Bus
÷ (8 × (DIV + 1)) Eqn. 4-2
Table 4-7 shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.
4.5.11.2 Flash and EEPROM Options Register (FOPT and NVOPT)
During reset, the contents of the nonvolatile location NVOPT are copied from Flash into FOPT. To change
the value in this register, erase and reprogram the NVOPT location in Flash memory as usual and then issue
a new MCU reset.
Table 4-6. FCDIV Register Field Descriptions
Field Description
7
DIVLD
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for Flash and EEPROM.
1 FCDIV has been written since reset; erase and program operations enabled for Flash and EEPROM.
6
PRDIV8
Prescale (Divide) Flash and EEPROM Clock by 8 (This bit is write once.)
0 Clock input to the Flash and EEPROM clock divider is the bus rate clock.
1 Clock input to the Flash and EEPROM clock divider is the bus rate clock divided by 8.
5:0
DIV
Divisor for Flash and EEPROM Clock Divider — These bits are write once. The Flash and EEPROM clock
divider divides the bus rate clock (or the bus rate clock divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV
field plus one. The resulting frequency of the internal Flash and EEPROM clock must fall within the range of
200 kHz to 150 kHz for proper Flash and EEPROM operations. Program/Erase timing pulses are one cycle of
this internal Flash and EEPROM clock which corresponds to a range of 5 μs to 6.7 μs. The automated
programming logic uses an integer number of these pulses to complete an erase or program operation. See
Equation 4-1 and Equation 4-2.
Table 4-7. Flash and EEPROM Clock Divider Settings
f
Bus
PRDIV8
(Binary)
DIV
(Decimal)
f
FCLK
Program/Erase Timing Pulse
(5 μs Min, 6.7 μs Max)
20 MHz 1 12 192.3 kHz 5.2 μs
10 MHz 0 49 200 kHz 5 μs
8 MHz 0 39 200 kHz 5 μs
4 MHz 0 19 200 kHz 5 μs
2 MHz 0 9 200 kHz 5 μs
1 MHz 0 4 200 kHz 5 μs
200 kHz 0 0 200 kHz 5 μs
150 kHz 0 0 150 kHz 6.7 μs