Datasheet

Appendix B Timer Pulse-Width Modulator (TPMV2)
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 343
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to
ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers,
TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers. Values are
transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have
been written and the timer counter overflows (reverses direction from up-counting to down-counting at the
end of the terminal count in the modulus register). This TPMxCNT overflow requirement only applies to
PWM channels, not output compares.
Optionally, when TPMxCNTH:TPMxCNTL = TPMxMODH:TPMxMODL, the TPM can generate a TOF
interrupt at the end of this count. The user can choose to reload any number of the PWM buffers, and they
will all update simultaneously at the start of a new period.
Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the
coherency mechanism for the modulo registers. Writing to TPMxCnSC cancels any values written to the
channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL.
B.4 TPM Interrupts
The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel.
The meaning of channel interrupts depends on the mode of operation for each channel. If the channel is
configured for input capture, the interrupt flag is set each time the selected input capture edge is
recognized. If the channel is configured for output compare or PWM modes, the interrupt flag is set each
time the main timer counter matches the value in the 16-bit channel value register. See the Resets,
Interrupts, and System Configuration chapter for absolute interrupt vector addresses, priority, and local
interrupt mask control bits.
For each interrupt source in the TPM, a flag bit is set on recognition of the interrupt condition such as timer
overflow, channel input capture, or output compare events. This flag may be read (polled) by software to
verify that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable
hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will be generated
whenever the associated interrupt flag equals 1. It is the responsibility of user software to perform a
sequence of steps to clear the interrupt flag before returning from the interrupt service routine.
B.4.1 Clearing Timer Interrupt Flags
TPM interrupt flags are cleared by a 2-step process that includes a read of the flag bit while it is set (1)
followed by a write of 0 to the bit. If a new event is detected between these two steps, the sequence is reset
and the interrupt flag remains set after the second step to avoid the possibility of missing the new event.
B.4.2 Timer Overflow Interrupt Description
The conditions that cause TOF to become set depend on the counting mode (up or up/down). In
up-counting mode, the 16-bit timer counter counts from 0x0000 through 0xFFFF and overflows to 0x0000
on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus
limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When
the counter is operating in up-/down-counting mode, the TOF flag gets set as the counter changes direction