Datasheet

Appendix B Timer Pulse-Width Modulator (TPMV2)
MC9S08DN60 Series Data Sheet, Rev 3
336 Freescale Semiconductor
When background mode is active, the timer counter and the coherency mechanism are frozen such that the
buffer latches remain in the state they were in when the background mode became active even if one or
both bytes of the counter are read while background mode is active.
B.2.3 Timer Counter Modulo Registers (TPMxMODH:TPMxMODL)
The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock
(CPWMS = 0) or starts counting down (CPWMS = 1), and the overflow flag (TOF) becomes set. Writing
to TPMxMODH or TPMxMODL inhibits TOF and overflow interrupts until the other byte is written. Reset
sets the TPM counter modulo registers to 0x0000, which results in a free-running timer counter (modulo
disabled).
It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well
before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM
modulo registers to avoid confusion about when the first counter overflow will occur.
76543210
R Bit 7 654321Bit 0
W Any write to TPMxCNTL clears the 16-bit counter.
Reset 00000000
Figure B-4. Timer Counter Register Low (TPMxCNTL)
76543210
R
Bit 15 14 13 12 11 10 9 Bit 8
W
Reset 00000000
Figure B-5. Timer Counter Modulo Register High (TPMxMODH)
76543210
R
Bit 7 654321Bit 0
W
Reset 00000000
Figure B-6. Timer Counter Modulo Register Low (TPMxMODL)