Datasheet

Appendix A Electrical Characteristics
MC9S08DN60 Series Data Sheet, Rev 3
326 Freescale Semiconductor
A.12.3 SPI
Table A-15 and Figure A-7 through Figure A-10 describe the timing requirements for the SPI system.
Table A-15. SPI Electrical Characteristic
Num
1
1
Refer to Figure A-7 through Figure A-10.
C Rating
2
2
All timing is shown with respect to 20% V
DD
and 70% V
DD
, unless noted; 100 pF load on all SPI
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
Symbol Min Max Unit
1D
Cycle time
Master
Slave
t
SCK
t
SCK
2
4
2048
—
t
cyc
t
cyc
2D
Enable lead time
Master
Slave
t
Lead
t
Lead
—
1/2
1/2
—
t
SCK
t
SCK
3D
Enable lag time
Master
Slave
t
Lag
t
Lag
—
1/2
1/2
—
t
SCK
t
SCK
4D
Clock (SPSCK) high time
Master and Slave
t
SCKH
(1/2 t
SCK
)– 25 — ns
5D
Clock (SPSCK) low time
Master and Slave
t
SCKL
(1/2 t
SCK
) – 25 — ns
6D
Data setup time (inputs)
Master
Slave
t
SI(M)
t
SI(S)
30
30
—
—
ns
ns
7D
Data hold time (inputs)
Master
Slave
t
HI(M)
t
HI(S)
30
30
—
—
ns
ns
8D
Access time, slave
3
3
Time to data active from high-impedance state.
t
A
040ns
9D
Disable time, slave
4
4
Hold time to high-impedance state.
t
dis
—40ns
10 D
Data setup time (outputs)
Master
Slave
t
SO
t
SO
25
25
—
—
ns
ns
11 D
Data hold time (outputs)
Master
Slave
t
HO
t
HO
–10
–10
—
—
ns
ns
12 D
Operating frequency
5
Master
Slave
5
Maximum baud rate must be limited to 5 MHz due to pad input characteristics.
f
op
f
op
f
Bus
/2048
dc
5
f
Bus
/4
MHz