Datasheet

Chapter 2 Pins and Connections
MC9S08DN60 Series Data Sheet, Rev 3
30 Freescale Semiconductor
3
Pin
Number
<-- Lowest Priority --> Highest
64 48 32
Port
Pin/Interrupt
Alt 1 Alt 2
1 1 — PTB6 PIB6 ADP14
2 — — PTC5
3 2 1 PTA7 PIA7 ADP7 IRQ
4 — — PTC6
5 3 — PTB7 PIB7 ADP15
6 — — PTC7
742 V
DD
853 V
SS
9 6 4 PTG0 EXTAL
10 7 5 PTG1 XTAL
11 8 6
RESET
12 9 — PTF4 ACMP2+
13 10 — PTF5 ACMP2-
14 — — PTF6 ACMP2O
15 11 7 PTE0 TxD1
16 12 8 PTE1
2
RxD1
2
17 13 9 PTE2 SS
18 14 10 PTE3 SPSCK
19 15 11 PTE4 SCL
3
MOSI
20 16 12 PTE5 SDA
3
MISO
21 — — PTG2
22 — — PTG3
23 17 — PTF0
24 18 — PTF1
25 19 — PTF2 TPM1CLK SCL
3
26 20 — PTF3 TPM2CLK SDA
3
27 — — PTG4
28 — — PTG5
29 21 13 PTE6
30 22 14 PTE7
31 23 15 PTD0 PID0 TPM2CH0
32 24 16 PTD1 PID1 TPM2CH1
33 25 17 PTD2 PID2 TPM1CH0
34 26 18 PTD3 PID3 TPM1CH1
35 27 19 PTD4 PID4 TPM1CH2
36 28 20 PTD5 PID5 TPM1CH3
37 — — PTF7
38 29 — V
SS
39 30 — V
DD
40 31 — PTD6 PID6 TPM1CH4
41 32 — PTD7 PID7 TPM1CH5
42 33 21 BKGD MS
43 — — PTC0
44 34 22 PTB0 PIB0 ADP8
45 — — PTC1
46 35 23 PTA0 PIA0 ADP0 MCLK
47 — — PTC2
48 36 24 PTB1 PIB1 ADP9
49 37 25 PTA1 PIA1 ADP1
1
ACMP1+
1
50 38 — PTB2 PIB2 ADP10
51 39 26 PTA2 PIA2 ADP2
1
ACMP1-
1
52 — — PTC3
53 40 — PTB3 PIB3 ADP11
54 41 27 PTA3 PIA3 ADP3 ACMP1O
55
42 28
V
SSA
56 V
REFL
57
43 29
V
REFH
58 V
DDA
59 44 30 PTA4 PIA4 ADP4
60 45 — PTB4 PIB4 ADP12
61 — — PTC4
62 46 31 PTA5 PIA5 ADP5
63 47 — PTB5 PIB5 ADP13
64 48 32 PTA6 PIA6 ADP6
Pin
Number
<-- Lowest Priority --> Highest
64 48 32
Port
Pin/Interrupt
Alt 1 Alt 2
Table 2-1. Pin Availability by Package Pin-Count
1. If both of these analog modules are enabled, they both will have access to the pin.
2. Pin does not contain a clamp diode to V
DD
and should not be driven above V
DD
. The voltage measured on this pin when internal
pull-up is enabled may be as low as V
DD
– 0.7 V. The internal gates connected to this pin are pulled to V
DD
.
3. The IIC module pins can be repositioned using IICPS bit in the SOPT1 register. The default reset locations are on PTF2 and PTF3.