Datasheet

Chapter 13 Serial Communications Interface (S08SCIV4)
MC9S08DN60 Series Data Sheet, Rev 3
242 Freescale Semiconductor
Figure 13-12. SCI Baud Rate Generation
SCI communications require the transmitter and receiver (which typically derive baud rates from
independent clock sources) to use the same baud rate. Allowed tolerance on this baud frequency depends
on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is
performed.
The MCU resynchronizes to bit boundaries on every high-to-low transition, but in the worst case, there are
no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is
accumulated for the whole character time. For a Freescale Semiconductor SCI system whose bus
frequency is driven by a crystal, the allowed baud rate mismatch is about 4.5percent for 8-bit data format
and about 4 percent for 9-bit data format. Although baud rate modulo divider settings do not always
produce baud rates that exactly match standard rates, it is normally possible to get within a few percent,
which is acceptable for reliable communications.
13.3.2 Transmitter Functional Description
This section describes the overall block diagram for the SCI transmitter, as well as specialized functions
for sending break and idle characters. The transmitter block diagram is shown in Figure 13-2.
The transmitter output (TxD) idle state defaults to logic high (TXINV = 0 following reset). The transmitter
output is inverted by setting TXINV = 1. The transmitter is enabled by setting the TE bit in SCI1C2. This
queues a preamble character that is one full character frame of the idle state. The transmitter then remains
idle until data is available in the transmit data buffer. Programs store data into the transmit data buffer by
writing to the SCI data register (SCI1D).
The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long
depending on the setting in the M control bit. For the remainder of this section, we will assume M = 0,
selecting the normal 8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits,
and a stop bit. When the transmit shift register is available for a new SCI character, the value waiting in
the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the
transmit data register empty (TDRE) status flag is set to indicate another character may be written to the
transmit data buffer at SCI1D.
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the
transmitter sets the transmit complete flag and enters an idle mode, with TxD high, waiting for more
characters to transmit.
SBR12:SBR0
DIVIDE BY
Tx BAUD RATE
Rx SAMPLING CLOCK
(16 × BAUD RATE)
BAUD RATE GENERATOR
OFF IF [SBR12:SBR0] = 0
BUSCLK
BAUD RATE =
BUSCLK
[SBR12:SBR0] × 16
16
MODULO DIVIDE BY
(1 THROUGH 8191)