Datasheet

Chapter 12 Serial Peripheral Interface (S08SPIV3)
MC9S08DN60 Series Data Sheet, Rev 3
226 Freescale Semiconductor
in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a
specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input
of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a
master and the MISO waveform applies to the MISO output from a slave. The
SS OUT waveform applies
to the slave select output from a master (provided MODFEN and SSOE = 1). The master
SS output goes
to active low at the start of the first bit time of the transfer and goes back high one-half SPSCK cycle after
the end of the eighth bit time of the transfer. The
SS IN waveform applies to the slave select input of a
slave.
Figure 12-11. SPI Clock Formats (CPHA = 0)
When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB
depending on LSBFE) when
SS goes to active low. The first SPSCK edge causes both the master and the
slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK
edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the
second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and
slave, respectively. When CPHA = 0, the slave’s
SS input must go to its inactive high level between
transfers.
BIT TIME #
(REFERENCE)
MSB FIRST
LSB FIRST
SPSCK
(CPOL = 0)
SPSCK
(CPOL = 1)
SAMPLE IN
(MISO OR MOSI)
MOSI
(MASTER OUT)
MISO
(SLAVE OUT)
SS OUT
(MASTER)
SS IN
(SLAVE)
BIT 7
BIT 0
BIT 6
BIT 1
BIT 2
BIT 5
BIT 1
BIT 6
BIT 0
BIT 7
12 67 8...
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