Datasheet

Modulo Timer (RS08MTIMV1)
MC9RS08KA2 Series Data Sheet, Rev. 4
92 Freescale Semiconductor
11.3.1 MTIM Status and Control Register (MTIMSC)
MTIMSC contains the overflow status flag and control bits which are used to configure the interrupt
enable, reset the counter, and stop the counter.
Table 11-2. MTIM Register Summary
Name
76543210
MTIMSC
RTOF
TOIE
0
TSTP
0000
W TRST
MTIMCLK
R0 0
CLKS PS
W
MTIMCNT
RCOUNT
W
MTIMMOD
R
MOD
W
7 6543210
R TOF
TOIE
0
TSTP
0000
W TRST
Reset: 0 0 0 1 0 0 0 0
Figure 11-3. MTIM Status and Control Register (MTIMSC)
Table 11-3. MTIMSC Field Descriptions
Field Description
7
TOF
MTIM Overflow Flag — This read-only bit is set when the MTIM counter register overflows to $00 after reaching
the value in the MTIM modulo register. Clear TOF by reading the MTIMSC register while TOF is set, then writing
a 0 to TOF. TOF is also cleared when TRST is written to a 1 or when any value is written to the MTIMMOD
register.
0 MTIM counter has not reached the overflow value in the MTIM modulo register.
1 MTIM counter has reached the overflow value in the MTIM modulo register.
6
TOIE
MTIM Overflow Interrupt Enable — This read/write bit enables MTIM overflow interrupts. If TOIE is set, then an
interrupt is generated when TOF = 1. Reset clears TOIE. Do not set TOIE if TOF = 1. Clear TOF first, then set
TOIE.
0 TOF interrupts are disabled. Use software polling.
1 TOF interrupts are enabled.
5
TRST
MTIM Counter Reset — When a 1 is written to this write-only bit, the MTIM counter register resets to $00 and
TOF is cleared. Reading this bit always returns 0.
0 No effect. MTIM counter remains at current state.
1 MTIM counter is reset to $00.
4
TSTP
MTIM Counter Stop — When set, this read/write bit stops the MTIM counter at its current value. Counting
resumes from the current value when TSTP is cleared. Reset sets TSTP to prevent the MTIM from counting.
0 MTIM counter is active.
1 MTIM counter is stopped.