Datasheet

Modulo Timer (RS08MTIMV1)
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 91
11.1.3 Block Diagram
The block diagram for the modulo timer module is shown Figure 11-2.
Figure 11-2. Modulo Timer (MTIM) Block Diagram
11.2 External Signal Description
The MTIM includes one external signal, TCLK, used to input an external clock when selected as the
MTIM clock source. The signal properties of TCLK are shown in Table 11-1.
The TCLK input must be synchronized by the bus clock. Also, variations in duty cycle and clock jitter
must be accommodated. Therefore, the TCLK signal must be limited to one-fourth of the bus frequency.
The TCLK pin can be muxed with a general-purpose port pin. See the Pins and Connections chapter for
the pin location and priority of this function.
11.3 Register Definition
Each MTIM includes four registers, which are summarized in Table 11-2:
• An 8-bit status and control register
• An 8-bit clock configuration register
• An 8-bit counter register
• An 8-bit modulo register
Refer to the direct-page register summary in the memory section of this data sheet for the absolute address
assignments for all MTIM registers. This section refers to registers and control bits only by their names.
Table 11-1. Signal Properties
Signal Function I/O
TCLK External clock source input into MTIM I
BUSCLK
TCLK
SYNC
CLOCK
SOURCE
SELECT
PRESCALE AND
SELECT DIVIDE
BY
8-BIT MODULO
(MTIMMOD)
8-BIT COMPARATOR
TRST
TSTP
CLKS
PS
XCLK
TOIE
MTIM
INTERRUPT
REQUEST
TOF
8-BIT COUNTER
(MTIMCNT)