Datasheet

Internal Clock Source (RS08ICSV1)
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 79
9.3.3 ICS Trim Register (ICSTRM)
9.3.4 ICS Status and Control (ICSSC)
7 6543210
R
TRIM
W
POR: 1 0 0 0 0 0 0 0
Reset:U UUUUUUU
Figure 9-5. ICS Trim Register (ICSTRM)
Table 9-4. ICSTRM Field Descriptions
Field Description
7:0
TRIM
ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
7 6543210
R 0 0 0 0 0 CLKST 0
FTRIM
W
POR: 0 0 0 0 0 0 0 0
Reset: 0 0 0 0 0 0 0 U
= Unimplemented
Figure 9-6. ICS Status and Control Register (ICSSC)
Table 9-5. ICSSC Field Descriptions
Field Description
2
CLKST
Clock Mode Status — The CLKST read-only bit indicate the current clock mode. The CLKST bit does not update
immediately after a write to the CLKS bit due to internal synchronization between clock domains.
0 Output of FLL is selected
1 Internal reference clock is selected
0
FTRIM
ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.
Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount
possible.