Datasheet

Chapter 8 Central Processor Unit (RS08CPUV1)
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 71
LDX #opr8i
(1)
LDX opr8a
(1)
LDX ,X
(1)
Load Index Register from
Memory
$0F ← (M)
¦ —
IMD
DIR
IX
3E
4E
4E
ii 0F
dd 0F
0E 0E
4
5
5
LSLA
Logical Shift Left
¦¦INH 48 1
LSRA
Logical Shift Right
¦¦INH 44 1
MOV opr8a,opr8a
MOV #opr8i,opr8a
MOV D[X],opr8a
MOV opr8a,D[X]
MOV #opr8i,D[X]
Move (M)
destination
← (M)
source
¦ —
DD
IMD
IX/DIR
DIR/IX
IMM/IX
4E
3E
4E
4E
3E
dd dd
ii dd
0E dd
dd 0E
ii 0E
5
4
5
5
4
NOP No Operation None
——INH AC 1
ORA #opr8i
ORA opr8a
ORA ,X
(1)
ORA X
Inclusive OR
Accumulator and
Memory
A ← (A) | (M)
A ← (A) | (X)
¦ —
IMM
DIR
IX
DIR
AA
BA
BA
BA
ii
dd
0E
0F
2
3
3
3
ROLA
Rotate Left through Carry
¦¦INH 49 1
RORA Rotate Right through
Carry
¦¦INH 46 1
RTS Return from Subroutine Pull PC from shadow PC
——INH BE 3
SBC #opr8i
SBC opr8a
SBC ,X
(1)
SBC X
Subtract with Carry
A ← (A) – (M) – (C)
A ← (A) – (X) – (C)
¦¦
IMM
DIR
IX
DIR
A2
B2
B2
B2
ii
dd
0E
0F
2
3
3
3
SEC Set Carry Bit C ← 1
—1 INH 39 1
SHA
Swap Shadow PC High
with A
A ⇔ SPCH
——INH 45 1
SLA
Swap Shadow PC Low
with A
A ⇔ SPCL
——INH 42 1
STA opr8a
STA opr5a
STA ,X
(1)
STA X
Store Accumulator in
Memory
M ← (A)
¦ —
DIR
SRT
IX
SRT
B7
Ex / Fx
EE
EF
dd
3
2
2
2
STX opr8a
(1)
Store Index Register in
Memory
M ← (X)
¦ — DIR 4E 0F dd 5
STOP Put MCU into stop mode
——INH AE 2+
Table 8-1. Instruction Set Summary (Sheet 5 of 6)
Source
Form
Description Operation
Effect
on
CCR
Address
Mode
Opcode
Operand
Cycles
ZC
1. This is a pseudo instruction supported by the normal RS08 instruction set.
2. This instruction is different from that of the HC08 and HCS08 in that the RS08 does not auto-increment the index register.
C
b0
b7
0
b0
b7
C0
C
b0
b7
b0
b7
C