Datasheet
Chapter 8 Central Processor Unit (RS08CPUV1)
MC9RS08KA2 Series Data Sheet, Rev. 4
68 Freescale Semiconductor
BHS rel
(1)
Branch if Higher or Same
(Same as BCC)
PC ← (PC) + $0002 + rel, if (C) = 0
——
REL 34 rr 3
BLO rel
(1)
Branch if Lower (Same
as BCS)
PC ← (PC) + $0002 + rel, if (C) = 1
——
REL 35 rr 3
BNE rel Branch if Not Equal PC ← (PC) + $0002 + rel, if (Z) = 0
—
—
REL 36 rr 3
BRA rel Branch Always PC ← (PC) + $0002 + rel
—
—
REL 30 rr 3
BRN rel
(1)
Branch Never PC ← (PC) + $0002
—
—
REL 30 00 3
BRCLR n,opr8a,rel
BRCLR n,D[X],rel
BRCLR n,X,rel
Branch if Bit n in Memory
Clear
PC ← (PC) + $0003 + rel, if (Mn) = 0
— ¦
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
IX (b0)
IX (b1)
IX (b2)
IX (b3)
IX (b4)
IX (b5)
IX (b6)
IX (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
01
03
05
07
09
0B
0D
0F
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
0E rr
0E rr
0E rr
0E rr
0E rr
0E rr
0E rr
0E rr
0F rr
0F rr
0F rr
0F rr
0F rr
0F rr
0F rr
0F rr
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Table 8-1. Instruction Set Summary (Sheet 2 of 6)
Source
Form
Description Operation
Effect
on
CCR
Address
Mode
Opcode
Operand
Cycles
ZC
1. This is a pseudo instruction supported by the normal RS08 instruction set.
2. This instruction is different from that of the HC08 and HCS08 in that the RS08 does not auto-increment the index register.