Datasheet

Chapter 8 Central Processor Unit (RS08CPUV1)
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 67
Table 8-1. Instruction Set Summary (Sheet 1 of 6)
Source
Form
Description Operation
Effect
on
CCR
Address
Mode
Opcode
Operand
Cycles
ZC
ADC #opr8i
ADC opr8a
ADC ,X
(1)
ADC X
Add with Carry
A ← (A) + (M) + (C)
A ← (A) + (X) + (C)
¦¦
IMM
DIR
IX
DIR
A9
B9
B9
B9
ii
dd
0E
0F
2
3
3
3
ADD #opr8i
ADD opr8a
ADD opr4a
ADD ,X
(1)
ADD X
Add without Carry A ← (A) + (M)
¦¦
IMM
DIR
TNY
IX
DIR
AB
BB
6x
6E
6F
ii
dd
2
3
3
3
3
AND #opr8i
AND opr8a
AND ,X
(1)
AND X
Logical AND
A ← (A) & (M)
A ← (A) & (X)
¦
—
IMM
DIR
IX
DIR
A4
B4
B4
B4
ii
dd
0E
0F
2
3
3
3
ASLA
(1)
Arithmetic Shift Left
¦¦INH 48
1
BCC rel Branch if Carry Bit Clear PC ← (PC) + $0002 + rel, if (C) = 0 — —
REL 34 rr
3
BCLR n,opr8a
BCLR n,D[X]
BCLR n,X
Clear Bit n in Memory Mn ← 0
——
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
IX (b0)
IX (b1)
IX (b2)
IX (b3)
IX (b4)
IX (b5)
IX (b6)
IX (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
11
13
15
17
19
1B
1D
1F
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
0E
0E
0E
0E
0E
0E
0E
0E
0F
0F
0F
0F
0F
0F
0F
0F
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
BCS rel
Branch if Carry Bit Set
(Same as BLO)
PC ← (PC) + $0002 + rel, if (C) = 1
——REL 35 rr
3
BEQ rel Branch if Equal PC ← (PC) + $0002 + rel, if (Z) = 1
——REL 37 rr
3
BGND Background Enter Background Debug Mode
——INH BF 5+
1. This is a pseudo instruction supported by the normal RS08 instruction set.
2. This instruction is different from that of the HC08 and HCS08 in that the RS08 does not auto-increment the index register.
C
b0
b7
0