Datasheet
Chapter 5 Resets, Interrupts, and General System Control
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 41
5.8.4 System Real-Time Interrupt Status and Control Register (SRTISC)
This high page register contains status and control bits for the RTI.
Table 5-4. SDIDH Register Field Descriptions
Field Description
7:4
REV[3:0]
Revision Number — The high-order 4 bits of address SDIDH are hard coded to reflect the current mask set
revision number (0–F).
3:0
ID[11:8]
Part Identification Number — Each derivative in the RS08 Family has a unique identification number. The
MC9RS08KA2 Series is hard coded to the value $0800. See also ID bits in Figure 5-4.
76543210
R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
W
Reset:00000000
= Unimplemented or Reserved
Figure 5-4. System Device Identification Register — Low (SDIDL)
Table 5-5. SDIDL Register Field Descriptions
Field Description
7:0
ID[7:0]
Part Identification Number — Each derivative in the RS08 Family has a unique identification number. The
MC9RS08KA2 Series is hard coded to the value $0800. See also ID bits in Figure 5-3.
76543210
RRTIF 0
RTICLKS RTIE
0
RTIS
W RTIACK
Reset:00000000
= Unimplemented or Reserved
Figure 5-5. System RTI Status and Control Register (SRTISC)
Table 5-6. SRTISC Register Field Descriptions
Field Description
7
RTIF
Real-Time Interrupt Flag — This read-only status bit indicates the periodic wakeup timer has timed out.
0 Periodic wakeup timer not timed out.
1 Periodic wakeup timer timed out.
6
RTIACK
Real-Time Interrupt Acknowledge — This write-only bit is used to acknowledge real-time interrupt request
(write 1 to clear RTIF). Writing 0 has no meaning or effect. Reads always return 0.
5
RTICLKS
Real-Time Interrupt Clock Select — This read/write bit selects the clock source for the real-time interrupt.
0 Real-time interrupt request clock source is internal 1-kHz oscillator.
1 Real-time interrupt request clock source is internal trimmed 32-kHz oscillator (ICS module) and is divided by
32 in RTI logic to produce a trimmed 1-kHz clock source for RTI counter.