Datasheet

Chapter 1 MC9RS08KA2 Series Device Overview

MC9RS08KA2 Series Data Sheet, Rev. 4

16 Freescale Semiconductor

Table 1-1 provides the functional versions of the on-chip modules.

1.3 System Clock Distribution

Figure 1-2. System Clock Distribution Diagram

Figure 1-2 shows a simplified clock connection diagram for the MCU. The bus clock frequency is half of

the ICS output frequency and is used by all of the internal modules.

Table 1-1. Block Versions

Module Version

Analog Comparator (ACMP) 1

Keyboard Interrupt (KBI) 1

Modulo Timer (MTIM) 1

Internal Clock Source (ICS) 1

MTIM

BDC

FLASH

ICS

BDCBDC

CPU

SYSTEM CONTROL LOGIC

RTI

RTICLKS

1-kHz

÷2

ICSOUT

ICSFFCLK

ICSIRCLK

FIXED CLOCK (XCLK)

BUS CLOCK

TCLK

COP

÷32

÷2

SYNC

The fixed clock (XCLK) is internally synchronized to the bus clock and must not exceed one half of the

bus clock frequency