Datasheet

Appendix A Electrical Characteristics
MC9RS08KA2 Series Data Sheet, Rev. 4
118 Freescale Semiconductor
A.9 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.9.1 Control Timing
Figure A-1. Reset Timing
Stop recovery time (FLL wakeup to previous acquired
frequency)
IREFSTEN=0
IREFSTEN=1
t_wakeup
t
ir_wu
t
fll_wu
—100
86
—
μs
1
Data in typical column was characterized at 3.0 V and 5.0 V, 25°C or is typical recommended value.
2
This parameter is characterized and not tested on each device.
3
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBILP) to FLL enabled (FEI, FBI).
Table A-8. Control Timing
Parameter Symbol Min Typical Max Unit
Bus frequency (t
cyc
= 1/f
Bus
)f
Bus
dc — 10 MHz
Real time interrupt internal oscillator period t
RTI
700 1000 1300 μs
External RESET pulse width
1
1
This is the shortest pulse that is guaranteed to pass through the pin input filter circuitry. Shorter pulses may or may not be
recognized.
t
extrst
150 — — ns
KBI pulse width
2
2
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
t
KBIPW
1.5 t
cyc
——ns
KBI pulse width in stop
1
t
KBIPWS
100 — — ns
Port rise and fall time (load = 50 pF)
3
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
3
Timing is shown with respect to 20% V
DD
and 80% V
DD
levels. Temperature range –40°C to 85°C.
t
Rise
, t
Fall
—
—
11
35
—
—
ns
Table A-7. Internal Clock Source Specifications
Characteristic Symbol Min Typ
1
Max Unit
t
extrst
RESET