MC9RS08KA2 MC9RS08KA1 Data Sheet RS08 Microcontrollers MC9RS08KA2 Rev. 4 12/2008 freescale.
MC9RS08KA2 Features 8-Bit RS08 Central Processor Unit (CPU) • • • • Simplified S08 instruction set with added high-performance instructions — LDA, STA, and CLR instructions support the short addressing mode; address $0000 to $001F can be accessed via a single-byte instruction — ADD, SUB, INC, and DEC instructions support the tiny addressing mode; address $0000 to $000F can be accessed via a single-byte instruction with reduced instruction cycle — Shadow PC register instructions: SHA and SLA Pending inter
MC9RS08KA2 Series Data Sheet, Rev.
MC9RS08KA2 Series Data Sheet Covers: MC9RS08KA2 MC9RS08KA1 MC9RS08KA2 Rev.
Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. Revision Number Revision Date 1.
List of Chapters Chapter List of Chapters Title Page Chapter 1 MC9RS08KA2 Series Device Overview ......................................... 15 Chapter 2 Pins and Connections ..................................................................... 17 Chapter 3 Modes of Operation ......................................................................... 21 Chapter 4 Memory.............................................................................................
Table of Contents Section Number Title Page Chapter 1 MC9RS08KA2 Series Device Overview 1.1 1.2 1.3 Overview .........................................................................................................................................15 MCU Block Diagram ......................................................................................................................15 System Clock Distribution ..............................................................................................
Section Number 4.7 4.8 Title Page 4.6.4 Security ...........................................................................................................................31 Flash Registers and Control Bits .....................................................................................................32 4.7.1 Flash Options Register (FOPT and NVOPT) .................................................................32 4.7.2 Flash Control Register (FLCR) ...............................................
Section Number 7.2 7.3 7.4 Title Page 7.1.3 Block Diagram ................................................................................................................52 External Signal Description ............................................................................................................52 Register Definition ..........................................................................................................................53 7.3.1 KBI Status and Control Register (KBISC) .....
Section Number Title Page Chapter 9 Internal Clock Source (RS08ICSV1) 9.1 9.2 9.3 9.4 Introduction .....................................................................................................................................75 9.1.1 Features ...........................................................................................................................76 9.1.2 Modes of Operation ........................................................................................................
Section Number Title Page Chapter 11 Modulo Timer (RS08MTIMV1) 11.1 Introduction .....................................................................................................................................89 11.1.1 Features ...........................................................................................................................90 11.1.2 Modes of Operation ........................................................................................................90 11.1.2.
Section Number Title Page Appendix A Electrical Characteristics A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 Introduction ...................................................................................................................................109 Absolute Maximum Ratings ..........................................................................................................109 Thermal Characteristics .....................................................................................................
Chapter 1 MC9RS08KA2 Series Device Overview 1.1 Overview The MC9RS08KA2 Series microcontroller unit (MCU) is an extremely low-cost, small pin count device for home appliances, toys, and small geometry applications. This device is composed of standard on-chip modules including, a very small and highly efficient RS08 CPU core, 63 bytes RAM, 2K bytes Flash, an 8-bit modulo timer, keyboard interrupt, and analog comparator. The device is available in small 6- and 8-pin packages. 1.
Chapter 1 MC9RS08KA2 Series Device Overview Table 1-1 provides the functional versions of the on-chip modules. Table 1-1. Block Versions Module 1.
Chapter 2 Pins and Connections 2.1 Introduction This chapter describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and a detailed discussion of signals. 2.2 Device Pin Assignment Figure 2-1 and Figure 2-3 show the pin assignments in the packages available for the MC9RS08KA2 Series. PTA2/KBIP2/TCLK/RESET/VPP 1 6 PTA0/KBIP0/ACMP+ PTA3/ACMPO/BKGD/MS 2 5 PTA1/KBIP1/ACMP- VDD 3 4 VSS Figure 2-1.
Chapter 2 Pins and Connections PTA2/KBIP2/TCLK/RESET/VPP 1 8 PTA0/KBIP0/ACMP+ PTA3/ACMPO/BKGD/MS 2 7 PTA1/KBIP1/ACMP- VDD 3 6 PTA4/KBIP4 VSS 4 5 PTA5/KBIP5 Figure 2-3. MC9RS08KA2 Series in 8-Pin Narrow Body SOIC 2.3 Recommended System Connections Figure 2-4 shows reference connection for background debug and Flash programming. VDD MC9RS08KA2 VDD CBUK 10 μF CBY 0.1 μF VSS VDD BKGD/MS BACKGROUND HEADER RESET/VPP PTA0/KBIP0/ACMP+ PTA1/KBIP1/ACMPPTA4/KBIP4 (Note 1) NOTES: 1.
Chapter 2 Pins and Connections 2.4.1 Power VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides a regulated lower-voltage source to the CPU and other internal circuitry of the MCU.
Chapter 2 Pins and Connections cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD pin. 2.4.4 General-Purpose I/O and Peripheral Ports The remaining pins are shared among general-purpose I/O and on-chip peripheral functions such as timers and analog comparator. Immediately after reset, all of these pins are configured as high-impedance general-purpose inputs with internal pullup/pulldown devices disabled.
Chapter 3 Modes of Operation 3.1 Introduction This chapter describes the operating modes of the MC9RS08KA2 Series are described in this chapter. It also details entry into each mode, exit from each mode, and functionality while in each of the modes. 3.2 • • • 3.
Chapter 3 Modes of Operation • When a BDC breakpoint is encountered After active background mode is entered, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running, can be issued through the BKGD pin while the MCU is in run mode.
Chapter 3 Modes of Operation Table 3-1 summarizes the behavior of the MCU in wait mode. Table 3-1. Wait Mode Behavior 3.6 Mode CPU Digital Peripherals ICS ACMP Regulator I/O Pins RTI Wait Standby Optionally on On Optionally on On States held Optionally on Stop Mode Stop mode is entered upon execution of a STOP instruction when the STOPE bit in the system option register is set. In stop mode, all internal clocks to the CPU and the modules are halted.
Chapter 3 Modes of Operation the IREFSTEN bit. For the ICS to run in stop, the LVDE and LVDSE bits in the SPMSC1 must both be set before entering stop. 3.6.1 Active BDM Enabled in Stop Mode Entry into active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. This register is described in the Development Support chapter of this data sheet.
Chapter 4 Memory 4.1 Memory Map The memory map of the MCU is divided into the following groups: • Fast access RAM using tiny and short instructions ($0000–$000E1) • Indirect data access D[X] ($000E) • Index register X for D[X] ($000F) • Frequently used peripheral registers ($0010–$001E) • PAGESEL register ($001F) • RAM ($0020–$004F) • Paging window ($00C0–$00FF) • Other peripheral registers ($0200–$023F) • Nonvolatile memory — MC9RS08KA2: $3800–$3FFF — MC9RS08KA1: $3C00—$3FFF 1.
Chapter 4 Memory $0000 $000D $000E $000F $0010 PAGE REGISTER CONTENT $00 FAST ACCESS RAM 14 BYTES $0000 $000D $000E $000F $0010 D[X] REGISTER X $001E $001F $0020 PAGESEL D[X] REGISTER X PAGESEL RAM 48 BYTES 48 BYTES $004F UNIMPLEMENTED UNIMPLEMENTED $00C0 $00C0 PAGING WINDOW PAGING WINDOW $00FF $00FF UNIMPLEMENTED UNIMPLEMENTED $08 (reset value) $0200 HIGH PAGE REGISTERS $08 (reset value) $0200 $023F HIGH PAGE REGISTERS UNIMPLEMENTED UNIMPLEMENTED $E0 $3800 FLASH 2044 BYTES $3FFB $
Chapter 4 Memory 4.2 Unimplemented Memory Attempting to access either data or an instruction at an unimplemented memory address will cause reset. 4.3 Indexed/Indirect Addressing Register D[X] and register X together perform the indirect data access. Register D[X] is mapped to address $000E. Register X is located in address $000F. The 8-bit register X contains the address that is used when register D[X] is accessed. Register X is cleared to zero upon reset.
Chapter 4 Memory Frequently used registers can make use of the short addressing mode instructions for faster load, store, and clear operations. For short addressing mode instructions, the operand is encoded along with the opcode to a single byte. Table 4-1.
Chapter 4 Memory Table 4-1.
Chapter 4 Memory • • 4.6.2 Up to 1000 program/erase cycles at typical voltage and temperature Security feature for Flash Flash Programming Procedure Programming of Flash memory is done on a row basis. A row consists of 64 consecutive bytes starting from addresses $3X00, $3X40, $3X80, or $3XC0. Use the following procedure to program a row of Flash memory: 1. Apply external VPP. 2. Set the PGM bit.
Chapter 4 Memory 3. Write any data to any Flash location, via the high page accessing window $00C0–$00FF. (Prior to the data writing operation, the PAGESEL register must be configured correctly to map the high page accessing window to the any Flash locations). 4. Wait for a time, tnvs. 5. Set the HVEN bit. 6. Wait for a time tme. 7. Clear the MASS bit. 8. Wait for a time, tnvh1. 9. Clear the HVEN bit. 10. After time, trcv, the memory can be accessed in read mode again. 11. Remove external VPP.
Chapter 4 Memory NOTE When the device boots up to normal operating mode, where MS pin is high during reset, with SECD programmed (SECD = 0), Flash security is engaged. BKGDPE is reset to 0, and all BDM communication is blocked, and background debug is not allowed. 4.7 Flash Registers and Control Bits The Flash module has a nonvolatile register, NVOPT ($3FFC), in Flash memory which is copied into the corresponding control register, FOPT ($0210), at reset. 4.7.
Chapter 4 Memory 4.7.2 Flash Control Register (FLCR) R 7 6 5 4 0 0 0 0 3 2 HVEN MASS 0 0 1 0 0 PGM1 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 4-4. Flash Control Register (FLCR) Table 4-3. FLCR Field Descriptions 1 Field Description 3 HVEN High Voltage Enable — This read/write bit enables high voltages to the Flash array for program and erase operations. HVEN can be set only if either PGM = 1 or MASS = 1 and the proper sequence for program or erase is followed.
Chapter 4 Memory 14-bit memory address Start address of memory block selected 0 0 0 0 0 0 AD[13:6] Figure 4-6. Memory Block Boundary Selector Table 4-5 shows the memory block to be accessed through paging window ($00C0–$00FF). Table 4-5. Paging Window for $00C0–$00FF Page Memory Address $00 $0000–$003F $01 $0040–$007F $02 $0080–$00BF $03 $00C0–$00FF $04 $0100–$013F . . . . . . $FE $3F80–$3FBF $FF $3FC0–$3FFF NOTE Physical location $0000-$000E is RAM.
Chapter 5 Resets, Interrupts, and General System Control 5.1 Introduction This chapter discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt in the MC9RS08KA2 Series. Some interrupt sources from peripheral modules are discussed in greater detail within other chapters of this data sheet. This chapter gathers basic information about all reset and interrupt sources in one place for easy reference.
Chapter 5 Resets, Interrupts, and General System Control • • • • Computer operating properly (COP) timer Illegal opcode detect (ILOP) Illegal address detect (ILAD) Background debug forced reset via BDC command BDC_RESET Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register (SRS). 5.
Chapter 5 Resets, Interrupts, and General System Control and ACMP are still available to wake the CPU from wait or stop mode. It is the responsibility of the user application to poll the corresponding module to determine the source of wakeup. Each wakeup source of the module is associated with a corresponding interrupt enable bit. If the bit is disabled, the interrupt source is gated, and that particular source cannot wake the CPU from wait or stop mode.
Chapter 5 Resets, Interrupts, and General System Control for applications requiring more accurate real-time interrupts. The RTICLKS bit in SRTISC is used to select the RTI clock source. Both the1-kHz and 32-kHz clock sources for the RTI can be used when the MCU is in run, wait or stop mode. For the 32-kHz clock source to run in stop, the LVDE and LVDSE bits in the SPMSC1 must both be set before entering stop.
Chapter 5 Resets, Interrupts, and General System Control Table 5-2. SRS Field Descriptions Field Description 7 POR Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while the internal supply was below the LVR threshold. 0 Reset not caused by POR. 1 POR caused reset.
Chapter 5 Resets, Interrupts, and General System Control Table 5-3. SOPT Register Field Descriptions Field Description 7 COPE COP Watchdog Enable — This write-once bit selects whether the COP watchdog is enabled. 0 COP watchdog timer disabled. 1 COP watchdog timer enabled (force reset on timeout). 6 COPT COP Watchdog Timeout — This write-once bit selects the timeout period of the COP. 0 Short timeout period selected. 1 Long timeout period selected.
Chapter 5 Resets, Interrupts, and General System Control Table 5-4. SDIDH Register Field Descriptions Field Description 7:4 REV[3:0] Revision Number — The high-order 4 bits of address SDIDH are hard coded to reflect the current mask set revision number (0–F). 3:0 ID[11:8] Part Identification Number — Each derivative in the RS08 Family has a unique identification number. The MC9RS08KA2 Series is hard coded to the value $0800. See also ID bits in Figure 5-4.
Chapter 5 Resets, Interrupts, and General System Control Table 5-6. SRTISC Register Field Descriptions (continued) Field Description 4 RTIE Real-Time Interrupt Enable — This read-write bit enables real-time interrupts. 0 Real-time interrupts disabled. 1 Real-time interrupts enabled. 2:0 RTIS Real-Time Interrupt Delay Selects — These read/write bits select the period for the RTI. See Table 5-7. Table 5-7.
Chapter 5 Resets, Interrupts, and General System Control 5.8.5 System Power Management Status and Control 1 Register (SPMSC1) This high page register contains status and control bits to support the low voltage detect function, and to enable the bandgap voltage reference for use by the ACMP and the LVD module.
Chapter 5 Resets, Interrupts, and General System Control 5.8.6 System Interrupt Pending Register (SIP1) This high page register contains status of the pending interrupt from the modules. R 7 6 5 4 3 2 1 0 0 0 0 KBI ACMP MTIM RTI LVD 0 0 0 0 0 0 0 0 W Reset: = Unimplemented or Reserved Figure 5-7. System Interrupt Pending Register (SIP1) Table 5-9.
Chapter 6 Parallel Input/Output Control This section explains software controls related to parallel input/output (I/O) and pin control. The MC9RS08KA2 Series has one parallel I/O port, which includes two I/O pins in the 6-pin package or four I/O pins in the 8-pin packages, one output-only pin, and one input-only pin. See Chapter 2, “Pins and Connections,” for more information about pin assignments and external hardware considerations for these pins.
Chapter 6 Parallel Input/Output Control When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function. However, the data direction register bit will continue to control the source for reads of the port data register. When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value of 0 is read for any port data bit where the bit is an input (PTADDn = 0) and the input buffer is disabled.
Chapter 6 Parallel Input/Output Control Table 6-1. PTAD Register Field Descriptions Field Description 5:0 PTAD[5:0] Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is driven out the corresponding MCU pin.
Chapter 6 Parallel Input/Output Control corresponding pulling device enable register bit. The pulling device is also disabled if the pin is controlled by an analog function. R 7 6 0 0 5 4 PTAPE5 PTAPE4 0 0 3 2 1 0 PTAPE2 PTAPE1 PTAPE0 0 0 0 0 W Reset: 0 0 0 Figure 6-4. Internal Pulling Device Enable for Port A Register (PTAPE) Table 6-3.
Chapter 6 Parallel Input/Output Control R 7 6 0 0 5 4 3 PTASE5 PTASE4 PTASE3 1 1 1 2 1 0 PTASE1 PTASE0 1 1 0 W Reset: 0 0 0 Figure 6-6. Slew Rate Enable for Port A Register (PTASE) Table 6-5. PTASE Register Field Descriptions Field Description 5:3;1:0 Output Slew Rate Enable for Port A Bits — Each of these control bits determines whether the output slew PTASE[5:3;1:0] rate control is enabled for the associated PTA pin.
Chapter 6 Parallel Input/Output Control MC9RS08KA2 Series Data Sheet, Rev.
Chapter 7 Keyboard Interrupt (RS08KBIV1) 7.1 Introduction The keyboard interrupt (KBI) module provides independently enabled external interrupt sources.
Chapter 7 Keyboard Interrupt (RS08KBIV1) 7.1.2 Modes of Operation This section defines the KBI operation in wait, stop, and background debug modes. 7.1.2.1 Operation in Wait Mode The KBI continues to operate in wait mode if enabled before executing the WAIT instruction. Therefore, an enabled KBI pin (KBPEn = 1) can be used to bring the MCU out of wait mode if the KBI interrupt is enabled (KBIE = 1). 7.1.2.
Chapter 7 Keyboard Interrupt (RS08KBIV1) 7.3 Register Definition The KBI includes three registers: • An 8-bit pin status and control register • An 8-bit pin enable register • An 8-bit edge select register Refer to the direct-page register summary in Chapter 4, “Memory,” for the absolute address assignments for all KBI registers. This section refers to registers and control bits only by their names. The KBI registers are summarized in Table 7-2. Table 7-2.
Chapter 7 Keyboard Interrupt (RS08KBIV1) Table 7-3. KBISC Register Field Descriptions (continued) Field Description 1 KBIE Keyboard Interrupt Enable — KBIE enables keyboard interrupt requests. 0 Keyboard interrupt request not enabled. 1 Keyboard interrupt request enabled. 0 KBMOD 7.3.2 Keyboard Detection Mode — KBMOD (along with the KBEDG bits) controls the detection mode of the keyboard interrupt pins. 0 Keyboard detects edges only. 1 Keyboard detects both edges and levels.
Chapter 7 Keyboard Interrupt (RS08KBIV1) 7.4 Functional Description This on-chip peripheral module is called a keyboard interrupt (KBI) module because it was originally designed to simplify the connection and use of row-column matrices of keyboard switches. However, these inputs are also useful as extra external interrupt inputs and as an external means of waking the MCU from stop or wait low-power modes. The KBI module allows its pins to act as additional interrupt sources.
Chapter 7 Keyboard Interrupt (RS08KBIV1) 5. Write to KBACK in KBISC to clear any false interrupts. 6. Set KBIE in KBISC to enable interrupts. MC9RS08KA2 Series Data Sheet, Rev.
Chapter 8 Central Processor Unit (RS08CPUV1) 8.1 Introduction This chapter is a summary of information about the registers, addressing modes, and instruction set of the RS08 Family CPU. For a more detailed discussion, refer to the RS08 Core Reference Manual, volume 1, Freescale Semiconductor document order number RS08RMv1.
Chapter 8 Central Processor Unit (RS08CPUV1) 7 0 ACCUMULATOR 13 A 0 8 7 PROGRAM COUNTER PC 13 0 SHADOW PROGRAM COUNTER SPC CONDITION CODE REGISTER Z C CCR CARRY ZERO Figure 8-1. CPU Registers In addition to the CPU registers, there are three memory mapped registers that are tightly coupled with the core address generation during data read and write operations. They are the indexed data register (D[X]), the index register (X), and the page select register (PAGESEL).
Chapter 8 Central Processor Unit (RS08CPUV1) 8.2.2 Program Counter (PC) The program counter is a 14-bit register that contains the address of the next instruction or operand to be fetched. During normal execution, the program counter automatically increments to the next sequential memory location each time an instruction or operand is fetched. Jump, branch, and return operations load the program counter with an address other than that of the next sequential location. This is called a change-of-flow.
Chapter 8 Central Processor Unit (RS08CPUV1) Other instructions may be executed between the test and the conditional branch as long as the only instructions used are those which do not disturb the CCR bits that affect the conditional branch. For instance, a test is performed in a subroutine or function and the conditional branch is not executed until the subroutine has returned to the main program.
Chapter 8 Central Processor Unit (RS08CPUV1) 8.2.7 Page Select Register (PAGESEL) This 8-bit page select register allows the user to access all memory locations in the entire 16K-byte address space through a page window located from $00C0 to $00FF. This register resides at the memory mapped location $001F. For details on the PAGESEL register, please refer to the RS08 Core Reference Manual. 8.
Chapter 8 Central Processor Unit (RS08CPUV1) expression in the operand field of the branch instruction; the assembler calculates the difference between the location counter (which points at the next address after the branch instruction at the time) and the address represented by the label or expression in the operand field. This difference is called the offset and is an 8-bit two’s complement number. The assembler stores this offset in the object code for the branch instruction.
Chapter 8 Central Processor Unit (RS08CPUV1) 8.3.5 Short Addressing Mode (SRT) SRT addressing mode is capable of addressing only the first 32 bytes in the address map, from $0000 to $001F. This addressing mode is available for CLR, LDA, and STA instructions. A system can be optimized by placing the most computation-intensive data in this area of memory.
Chapter 8 Central Processor Unit (RS08CPUV1) • • 8.4.1 Reset events force the CPU to start over at the beginning of the application program, which forces execution to start at $3FFD. A host development system can cause the CPU to go to active background mode rather than continuing to the next instruction in the application program. Reset Sequence Processing begins at the trailing edge of a reset event.
Chapter 8 Central Processor Unit (RS08CPUV1) 8.5 Summary Instruction Table Instruction Set Summary Nomenclature The nomenclature listed here is used in the instruction descriptions in Table 8-1 through Table 8-2.
Chapter 8 Central Processor Unit (RS08CPUV1) dd = ii hh ll rr = = = = Low-order eight bits of a direct address $0000–$00FF (high byte assumed to be $00) One byte of immediate data High-order 6-bit of 14-bit extended address prefixed with 2-bit of 0 Low-order byte of 14-bit extended address Relative offset Source form Everything in the source forms columns, except expressions in italic characters, is literal information which must appear in the assembly source file exactly as shown.
Chapter 8 Central Processor Unit (RS08CPUV1) ADC #opr8i ADC opr8a ADC ,X (1) ADC X ADD #opr8i ADD opr8a ADD opr4a ADD ,X (1) ADD X A ← (A) + (M) + (C) Add with Carry AND #opr8i AND opr8a AND ,X (1) AND X Logical AND ASLA(1) Arithmetic Shift Left ¦ ¦ INH 48 — — REL 34 11 13 15 17 19 1B 1D 1F 11 13 15 17 19 1B 1D 1F 11 13 15 17 19 1B 1D 1F rr dd dd dd dd dd dd dd dd 0E 0E 0E 0E 0E 0E 0E 0E 0F 0F 0F 0F 0F 0F 0F 0F 3 DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) IX (b0
Chapter 8 Central Processor Unit (RS08CPUV1) Cycles Operand Effect on CCR Z C Opcode Source Form Address Mode Table 8-1.
Chapter 8 Central Processor Unit (RS08CPUV1) BRSET n,opr8a,rel BRSET n,D[X],rel Branch if Bit n in Memory Set PC ← (PC) + $0003 + rel, if (Mn) = 1 BRSET n,X,rel BSET n,opr8a BSET n,D[X] Set Bit n in Memory Mn ← 1 BSET n,X DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) IX (b0) IX (b1) IX (b2) IX (b3) — ¦ IX (b4) IX (b5) IX (b6) IX (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR
Chapter 8 Central Processor Unit (RS08CPUV1) PC ← (PC) + 2 Push PC to shadow PC PC ← (PC) + rel BSR rel Branch Subroutine CBEQA #opr8i,rel CBEQ opr8a,rel CBEQ ,X,rel (1),(2) CBEQ X,rel (1) Compare and Branch if Equal CLC Clear Carry Bit PC ← (PC) + $0003 + rel, if (A) – (M) = $00 PC ← (PC) + $0003 + rel, if (A) – (M) = $00 PC ← (PC) + $0003 + rel, if (A) – (X) = $00 C←0 Cycles Operation Operand Description Effect on CCR Z C Opcode Source Form Address Mode Table 8-1.
Chapter 8 Central Processor Unit (RS08CPUV1) Table 8-1.
Chapter 8 Central Processor Unit (RS08CPUV1) SUB #opr8i SUB opr8a SUB opr4a SUB ,X (1) SUB X Subtract TAX(1) Transfer A to X TST opr8a TSTA (1) TST ,X (1) TSTX (1) A ← (A) – (M) IMM DIR ¦ TNY IX DIR — INH DD INH — IX INH — INH A0 B0 7x 7E 7F EF 4E AA 4E 4E CF — — INH AF ¦ A ← (A) – (X) X ← (A) ¦ (M) – $00 (A) – $00 (X) – $00 ¦ A ← (X) ¦ (1) Test for Zero TXA(1) Transfer X to A WAIT Put MCU into WAIT mode Cycles Operation Operand Description Effect on CCR Z C Opcode Source Form
Chapter 8 Central Processor Unit (RS08CPUV1) Table 8-2.
Chapter 8 Central Processor Unit (RS08CPUV1) MC9RS08KA2 Series Data Sheet, Rev.
Chapter 9 Internal Clock Source (RS08ICSV1) 9.1 Introduction The internal clock source (ICS) module provides clock source choices for the MCU. The module contains a frequency-locked loop (FLL) as a clock source that is controllable by an internal reference clock. The module can provide this FLL clock or the internal reference clock as a source for the MCU system clock, ICSOUT.
Internal Clock Source (RS08ICSV1) 9.1.1 Features Key features of the ICS module are: • Frequency-locked loop (FLL) is trimmable for accuracy — 0.
Internal Clock Source (RS08ICSV1) IREFSTEN ICSIRCLK CLKS BDIV Internal Reference Clock / 2n (32 kHz) ICSOUT1 n=0-3 LP 9 DCOOUT DCO TRIM ICSIRCLK /2 ICSFFCLK 9 Filter FLL 1 ICSOUT is two times the bus frequency Figure 9-2. Internal Clock Source (ICS) Block Diagram 9.2 External Signal Description No ICS signal connects off chip. 9.3 Register Definition Table 9-1 is a summary of ICS registers. Table 9-1.
Internal Clock Source (RS08ICSV1) 7 R 6 0 5 4 3 2 1 0 0 0 0 0 CLKS 0 IREFSTEN W Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure 9-3. ICS Control Register 1 (ICSC1) Table 9-2. ICSC1 Field Descriptions Field Description 6 CLKS Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency depends on the value of the BDIV bits.
Internal Clock Source (RS08ICSV1) 9.3.3 ICS Trim Register (ICSTRM) 7 6 5 4 3 2 1 0 R TRIM W POR: 1 0 0 0 0 0 0 0 Reset: U U U U U U U U Figure 9-5. ICS Trim Register (ICSTRM) Table 9-4. ICSTRM Field Descriptions Field Description 7:0 TRIM ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Internal Clock Source (RS08ICSV1) 9.4 9.4.1 Functional Description Operational Modes The states of the ICS are shown as a state diagram and are described in this section. The arrows indicate the allowed movements between the states. CLKS=1 LP=0 CLKS=0 FLL Engaged Internal (FEI) FLL Bypassed Internal (FBI) CLKS=1 LP=1 FLL Bypassed Internal Low Power(FBILP) Stop1, 2 1 ICS enters its Stop state when MCU enters stop, FLL is always disabled.
Internal Clock Source (RS08ICSV1) 9.4.1.4 Stop ICS stop mode is entered whenever the MCU enters stop. In this mode, all ICS clocks are stopped except ICSIRCLK which will remaining running if IREFSTEN is written to a 1. When the MCU is interrupted from stop, the ICS will go back to the operating mode that was running when the MCU entered stop. If the internal reference was not running in stop (IREFSTEN = 0), the ICS will take some time, tir_wu, for the internal reference to wakeup.
Internal Clock Source (RS08ICSV1) 9.4.6 Fixed Frequency Clock The ICS provides the ICSFFCLK output which can be used as an additional clock source to a peripheral such as a timer, when the ICS is in FEI. ICSFFCLK is not a valid clock source for a peripheral when in either FBI or FBILP modes. ICSFFCLK is ICSRCLK divided by two. MC9RS08KA2 Series Data Sheet, Rev.
Chapter 10 Analog Comparator (RS08ACMPV1) 10.1 Introduction The analog comparator module (ACMP) provides a circuit for comparing two analog input voltages or for comparing one analog input voltage to an internal reference voltage. The comparator circuit is designed to operate across the full range of the supply voltage (rail to rail operation). Figure 10-1 shows the MC9RS08KA2 Series block diagram with the ACMP highlighted.
Analog Comparator (RS08ACMPV1) 10.1.1 Features The ACMP has the following features: • Full rail-to-rail supply operation • Less than 40 mV of input offset • Less than 15 mV of hysteresis • Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output • Option to compare to fixed internal bandgap reference voltage • Option to allow comparator output to be visible on a pin, ACMPO • Remains operational in stop mode 10.1.
Analog Comparator (RS08ACMPV1) Internal Bus Internal Bandgap Reference Voltage ACIE ACBGS ACME Status and Control Register ACO set ACF ACME + Interrupt Control - ACMP- ACF ACOPE ACMOD ACMP+ ACMP INTERRUPT REQUEST Comparator ACMPO Figure 10-2. Analog Comparator (ACMP) Block Diagram MC9RS08KA2 Series Data Sheet, Rev.
Analog Comparator (RS08ACMPV1) 10.2 External Signal Description The ACMP has two analog input pins, ACMP+ and ACMP–, and one digital output pin, ACMPO. Each of the input pins can accept an input voltage that varies across the full operating voltage range of the MCU. As shown in Figure 10-2, the ACMP– pin is connected to the inverting input of the comparator, and the ACMP+ pin is connected to the non-inverting input of the comparator if ACBGS=0.
Analog Comparator (RS08ACMPV1) Table 10-2. ACMPSC Field Descriptions Field 7 ACME 6 ACBGS Description Analog Comparator Module Enable — ACME enables the ACMP module. 0 ACMP not enabled. 1 ACMP is enabled. Analog Comparator Bandgap Select — ACBGS is used to select between the internal bandgap reference voltage or the ACMP+ pin as the non-inverting input of the analog comparator. 0 External pin ACMP+ selected as non-inverting input to comparator.
Analog Comparator (RS08ACMPV1) NOTE Comparator inputs are high impedence analog pins which are sensitive to noise. Noisy VDD and/or pin toggling adjacent to the analog inputs may cause the comparator offset/hysteresis performance to exceed the specified values. Maximum source impedence is restricted to the value specified in Table A-6. To achieve maximum performance device is recommended to enter WAIT/STOP mode for ACMP measurement and adjacent pin toggling must be avoided.
Chapter 11 Modulo Timer (RS08MTIMV1) 11.1 Introduction The MTIM is a simple 8-bit timer with several software selectable clock sources and a programmable interrupt. The central component of the MTIM is the 8-bit counter that can operate as a free-running counter or a modulo counter. A timer overflow interrupt can be enabled to generate periodic interrupts for time-based software loops. The TCLK input is connected to the PTA2 pin of the MC9RS08KA2 Series.
Modulo Timer (RS08MTIMV1) 11.1.
Modulo Timer (RS08MTIMV1) 11.1.3 Block Diagram The block diagram for the modulo timer module is shown Figure 11-2. BUSCLK XCLK TCLK SYNC MTIM INTERRUPT REQUEST CLOCK SOURCE SELECT CLKS PRESCALE AND SELECT DIVIDE BY 8-BIT COUNTER (MTIMCNT) TRST TSTP 8-BIT COMPARATOR PS TOF 8-BIT MODULO (MTIMMOD) TOIE Figure 11-2. Modulo Timer (MTIM) Block Diagram 11.
Modulo Timer (RS08MTIMV1) Table 11-2. MTIM Register Summary Name 7 R 6 5 TOF 4 0 MTIMSC TOIE 2 1 0 0 0 0 0 TSTP W R 3 TRST 0 0 MTIMCLK CLKS PS W R COUNT MTIMCNT W R MTIMMOD MOD W 11.3.1 MTIM Status and Control Register (MTIMSC) MTIMSC contains the overflow status flag and control bits which are used to configure the interrupt enable, reset the counter, and stop the counter.
Modulo Timer (RS08MTIMV1) 11.3.2 MTIM Clock Configuration Register (MTIMCLK) MTIMCLK contains the clock select bits (CLKS) and the prescaler select bits (PS). R 7 6 0 0 5 4 3 2 CLKS 1 0 0 0 PS W Reset: 0 0 0 0 0 0 Figure 11-4. MTIM Clock Configuration Register (MTIMCLK) Table 11-4. MTIMCLK Field Description Field Description 5:4 CLKS Clock Source Select — These two read/write bits select one of four different clock sources as the input to the MTIM prescaler.
Modulo Timer (RS08MTIMV1) Table 11-5. MTIMCNT Field Description Field Description 7:0 COUNT MTIM Count — These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to this register. Reset clears the count to $00. 11.3.4 MTIM Modulo Register (MTIMMOD) 7 6 5 4 3 2 1 0 0 0 0 0 R MOD W Reset: 0 0 0 0 Figure 11-6. MTIM Modulo Register (MTIMMOD) Table 11-6.
Modulo Timer (RS08MTIMV1) 11.4 Functional Description The MTIM is composed of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector, and a prescaler block with nine selectable values. The module also contains software selectable interrupt logic. The MTIM counter (MTIMCNT) has three modes of operation: stopped, free-running, and modulo. Out of reset, the counter is stopped.
Modulo Timer (RS08MTIMV1) 11.4.1 MTIM Operation Example This section shows an example of the MTIM operation as the counter reaches a matching value from the modulo register. selected clock source MTIM clock (PS=%0010) MTIMCNT $A7 $A8 $A9 $AA $00 $01 TOF MTIMMOD: $AA Figure 11-7. MTIM Counter Overflow Example In the example of Figure 11-7, the selected clock source could be any of the four possible choices. The prescaler is set to PS = %0010 or divide-by-4.
Chapter 12 Development Support 12.1 Introduction Development support systems in the RS08 family include the RS08 background debug controller (BDC). The BDC provides a single-wire debug interface to the target MCU. This interface provides a convenient means for programming the on-chip FLASH and other nonvolatile memories.
Chapter 12 Development Support • • • • 12.
Chapter 12 Development Support BKGD 1 NO CONNECT 3 2 GND 4 RESET/VPP NO CONNECT 5 6 VDD Figure 12-2. Standard RS08 BDM Tool Connector Background debug controller (BDC) serial communications use a custom serial protocol that was first introduced on the M68HC12 Family of microcontrollers. This protocol requires that the host knows the communication clock rate, which is determined by the target BDC clock rate.
Chapter 12 Development Support The BDC serial communication protocol requires the host to know the target BDC clock speed. Commands and data are sent most significant bit first (MSB-first) at 16 BDC clock cycles per bit. The interface times out if 512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU system.
Chapter 12 Development Support BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN TARGET MCU SPEEDUP PULSE HIGH IMPEDANCE HIGH IMPEDANCE HIGH IMPEDANCE PERCEIVED START OF BIT TIME BKGD PIN R-C RISE 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN Figure 12-4. BDC Target-to-Host Serial Bit Timing (Logic 1) Figure 12-5 shows the host receiving a logic 0 from the target MCU.
Chapter 12 Development Support BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN HIGH IMPEDANCE SPEEDUP PULSE TARGET MCU DRIVE AND SPEEDUP PULSE PERCEIVED START OF BIT TIME BKGD PIN 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN Figure 12-5. BDM Target-to-Host Serial Bit Timing (Logic 0) 12.3.3 SYNC and Serial Communication Timeout The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin.
Chapter 12 Development Support • Subsequent bits must occur within 512 BDC cycles of the last bit sent. 12.4 BDC Registers and Control Bits The BDC contains two non-CPU accessible registers: • The BDC status and control register (BDCSCR) is an 8-bit register containing control and status bits for the background debug controller. • The BDC breakpoint register (BDCBKPT) holds a 16-bit breakpoint match address.
Chapter 12 Development Support Table 12-1. BDCSCR Register Field Descriptions (continued) Field 5 BKPTEN Description BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) control bit and BDCBKPT match register are ignored 0 BDC breakpoint disabled. 1 BDC breakpoint enabled. 4 FTS Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the BDCBKPT match register.
Chapter 12 Development Support R 15 14 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Any Reset 0 0 = Unimplemented or Reserved Figure 12-7. BDC Breakpoint Match Register (BDCBKPT) 12.5 RS08 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target MCU. All commands and data are sent MSB-first using a custom BDC communications protocol.
Chapter 12 Development Support Table 12-2.
Chapter 12 Development Support Table 12-2.
Chapter 12 Development Support MC9RS08KA2 Series Data Sheet, Rev.
Appendix A Electrical Characteristics A.1 Introduction This chapter contains electrical and timing specifications. A.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table A-1 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this chapter.
Appendix A Electrical Characteristics A.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the MCU design.
Appendix A Electrical Characteristics PD = K ÷ (TJ + 273°C) Eqn. A-2 Solving Equation A-1 and Equation A-2 for K gives: K = PD × (TA + 273°C) + θJA × (PD)2 Eqn. A-3 where K is a constant pertaining to the particular part. K can be determined from Equation A-3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations 1 and 2 iteratively for any value of TA. A.
Appendix A Electrical Characteristics Table A-4. DC Characteristics (continued) (Temperature Range = –40 to 85°C Ambient) Parameter Symbol Min Typical Max Unit VIL — — 0.30 × VDD V Input low voltage (1.8 V ≤ VDD ≤ 2.3 V) (all digital inputs) VIL — — 0.30 × VDD V Input hysteresis (all digital inputs) Vhys 0.06 × VDD — — V Input leakage current (per pin) VIn = VDD or VSS, all input only pins |IIn| — 0.025 1.
Appendix A Electrical Characteristics Figure 12-8. Typical IOH vs. VDD-VOH VDD = 5 V Figure 12-9. Typical IOH vs. VDD-VOH VDD = 3 V Figure 12-10. Typical IOH vs. VDD-VOH VDD = 1.8 V MC9RS08KA2 Series Data Sheet, Rev.
Appendix A Electrical Characteristics Figure 12-11. Typical IOL vs. VOL VDD = 5 V Figure 12-12. Typical IOL vs. VOL VDD = 3 V Figure 12-13. Typical VDD-VOH vs. VDD at IOH=2mA MC9RS08KA2 Series Data Sheet, Rev.
Appendix A Electrical Characteristics Figure 12-14. Typical VOL vs. VDD at IOL=2mA A.6 Supply Current Characteristics Table A-5. Supply Current Characteristics Parameter Symbol VDD (V) Typical1 Max2 Temp. (°C) RIDD10 5 5.6 mA 5.8 mA 6.5 mA 25 85 3 4.7 mA 4.8 mA 5.5 mA 25 85 1.8 2.3 mA 2.4 mA 3 mA 25 85 5 1 mA 1.1 mA 1.5 mA 25 85 3 0.9 mA 0.95 mA 1.2 mA 25 85 1.8 0.6 mA 0.62 mA 0.8 mA 25 85 5 1 μA 3 μA 2 μA 5 μA 25 85 3 0.9 μA 2.5 μA 2 μA 5 μA 25 85 1.8 0.
Appendix A Electrical Characteristics Table A-5. Supply Current Characteristics (continued) Parameter Symbol VDD (V) Typical1 Max2 5 15 μA 20 μA Temp. (°C) 25 85 ACMP adder from stop (ACME = 1) — 3 15 μA 20 μA 25 85 1.8 15 μA 20 μA 25 85 RTI adder from stop with 1-kHz clock source enabled4 — RTI adder from stop with 32-kHz ICS internal clock source reference enabled LVI adder from stop (LVDE=1 and LVDSE=1) — — 5 300 nA 500 nA 25 85 3 300 nA 500 nA 25 85 1.
Appendix A Electrical Characteristics Figure 12-15. Typical Run IDD vs. VDD for FEI mode A.7 Analog Comparator (ACMP) Electricals Table A-6. Analog Comparator Electrical Specifications Characteristic Symbol Min Typical Max Unit Supply voltage VDD 1.80 — 5.5 V Analog input voltage VAIN VSS – 0.3 — VDD V Analog source impedance RAS — — 10 kΩ Analog input offset voltage1 VAIO — 20 40 mV Analog Comparator hysteresis1 VH 3.0 9.0 15.
Appendix A Electrical Characteristics Table A-7. Internal Clock Source Specifications Characteristic Symbol Stop recovery time (FLL wakeup to previous acquired frequency) IREFSTEN=0 IREFSTEN=1 Min Typ1 Max — 100 86 — Unit t_wakeup tir_wu tfll_wu μs 1 Data in typical column was characterized at 3.0 V and 5.0 V, 25°C or is typical recommended value. This parameter is characterized and not tested on each device.
Appendix A Electrical Characteristics tKBIPWS tKBIPW KBI Pin (rising or high level) KBI Pin (falling or low level) tKBIPW tKBIPWS Figure A-2. KBI Pulse Width A.10 FLASH Specifications This section provides details about program/erase times and program-erase endurance for the FLASH memory. For detailed information about program/erase operations, see Chapter 4, “Memory.” MC9RS08KA2 Series Data Sheet, Rev.
Appendix A Electrical Characteristics Table A-9. FLASH Characteristics Symbol Min Typical1 Max Unit Supply voltage for program/erase VDD 2.7 — 5.5 V Program/Erase voltage VPP 11.8 12 12.2 V IVPP_prog IVPP_erase — — — — 200 100 μA μA VRead 1.8 — 5.
Appendix A Electrical Characteristics 100 Ω VPP 1 nF 12 V Figure A-3. Example VPP Filtering tprog WRITE DATA1 Data Next Data tpgs PGM tnvs tnvh trcv HVEN trs VPP2 tvps tvph thv 1 Next Data applies if programming multiple bytes in a single row, reference 4.6.2, “Flash Programming Procedure”. DD must be at a valid operating voltage before voltage is applied or removed from the VPP pin. 2V Figure A-4. Flash Program Timing MC9RS08KA2 Series Data Sheet, Rev.
Appendix A Electrical Characteristics tme trcv MASS tnvs tnvh1 HVEN trs VPP1 1V DD tvps tvph must be at a valid operating voltage before voltage is applied or removed from the VPP pin. Figure A-5. Flash Mass Erase Timing MC9RS08KA2 Series Data Sheet, Rev.
Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information This section contains ordering numbers for MC9RS08KA2 Series devices. See below for an example of the device numbering system. Table B-1. Device Numbering System Memory Package Device Number FLASH RAM Type 6 DFN DB 98ARL10602D 2 KB 1 KB 63 bytes 8 PDIP PC 98ASB42420B 8 NB-SOIC SC 98ASB42564B MC9RS08KA2 MC9RS08KA1 Designator Document No.
Appendix B Ordering Information and Mechanical Drawings MC9RS08KA2 Series Data Sheet, Rev.
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