Datasheet

Memory
MC68HC908QB8 Data Sheet, Rev. 3
26 Freescale Semiconductor
$0014
ESCI Status Register 2
(SCS2)
See page 129.
Read:000000BKFRPF
Write:
Reset:00000000
$0015
ESCI Data Register
(SCDR)
See page 129.
Read:R7R6R5R4R3R2R1R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
$0016
ESCI Baud Rate Register
(SCBR)
See page 130.
Read:
LINT LINR SCP1 SCP0 R SCR2 SCR1 SCR0
Write:
Reset:00000000
$0017
ESCI Prescaler Register
(SCPSC)
See page 131.
Read:
PDS2 PDS1 PDS0 PSSB4 PSSB3 PSSB2 PSSB1 PSSB0
Write:
Reset:00000000
$0018
ESCI Arbiter Control
Register (SCIACTL)
See page 135.
Read:
AM1
ALOST
AM0 ACLK
AFIN ARUN AROVFL ARD8
Write:
Reset:00000000
$0019
ESCI Arbiter Data Register
(SCIADAT)
See page 136.
Read: ARD7 ARD6 ARD5 ARD4 ARD3 ARD2 ARD1 ARD0
Write:
Reset:00000000
$001A
Keyboard Status and
Control Register (KBSCR)
See page 87.
Read: 0 0 0 0 KEYF 0
IMASKK MODEK
Write:
ACKK
Reset:00000000
$001B
Keyboard Interrupt
Enable Register (KBIER)
See page 88.
Read: 0
AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
Write:
Reset:00000000
$001C
Keyboard Interrupt Polarity
Register (KBIPR)
See page 88.
Read: 0 0
KBIP5 KBIP4 KBIP3 KBIP2 KBIP1 KBIP0
Write:
Reset:00000000
$001D
IRQ Status and Control
Register (INTSCR)
See page 81.
Read: 0 0 0 0 IRQF 0
IMASK MODE
Write:
ACK
Reset:00000000
$001E
Configuration Register 2
(CONFIG2)
(1)
See page 57.
Read:
IRQPUD IRQEN
RRRESCIBDSRC
OSCENIN-
STOP
RSTEN
Write:
Reset:00000000
(2)
1. One-time writable register after each reset.
2. RSTEN reset to 0 by a power-on reset (POR) only.
$001F
Configuration Register 1
(CONFIG1)
(1)
See page 58.
Read:
COPRS LVISTOP LVIRSTD LVIPWRD LVITRIP SSREC STOP COPD
Write:
Reset:00000
(2)
000
1. One-time writable register after each reset.
2. LVITRIP reset to 0 by a power-on reset (POR) only.
$0020
TIM Status and Control
Register (TSC)
See page 183.
Read: TOF
TOIE TSTOP
00
PS2 PS1 PS0
Write: 0 TRST
Reset:00100000
$0021
TIM Counter Register High
(TCNTH)
See page 185.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:00000000
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5)