Datasheet

5-V Control Timing
MC68HC908QB8 Data Sheet, Rev. 3
Freescale Semiconductor 211
18.7 5-V Control Timing
Figure 18-3. RST and IRQ Timing
Characteristic
(1)
1. V
DD
= 4.5 to 5.5 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
; timing shown with respect to 20% V
DD
and 70% V
SS
, unless otherwise
noted.
Symbol Min Max Unit
Internal operating frequency
f
OP
(f
BUS
)
—8MHz
Internal clock period (1/f
OP
)t
cyc
125 — ns
RST
input pulse width low
(2)
2. Values are based on characterization results, not tested in production.
t
RL
100 — ns
IRQ
interrupt pulse width low (edge-triggered)
(2)
t
ILIH
100 — ns
IRQ
interrupt pulse period
(2)
t
ILIL
Note
(3)
3. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 t
cyc
.
—t
cyc
RST
IRQ
t
RL
t
ILIH
t
ILIL