Datasheet

Development Support
MC68HC908QB8 Data Sheet, Rev. 3
200 Freescale Semiconductor
17.3.1.1 Normal Monitor Mode
RST
and OSC1 functions will be active on the PTA3 and PTA5 pins respectively as long as V
TST
is
applied to the IRQ
pin. If the IRQ pin is lowered (no longer V
TST
) then the chip will still be operating in
monitor mode, but the pin functions will be determined by the settings in the configuration registers (see
Chapter 5 Configuration Register (CONFIG)) when V
TST
was lowered. With V
TST
lowered, the BIH and
BIL instructions will read the IRQ
pin state only if IRQEN is set in the CONFIG2 register.
If monitor mode was entered with V
TST
on IRQ, then the COP is disabled as long as V
TST
is applied to
IRQ
.
Table 17-1. Monitor Mode Signal Requirements and Options
Mode
IRQ
(PTA2)
RST
(PTA3)
Reset
Vector
Serial
Communi-
cation
Mode
Selection
COP
Communication
Speed
Comments
PTA0 PTA1 PTA4
External
Clock
Bus
Frequency
Baud
Rate
Normal
Monitor
V
TST
V
DD
X110Disabled
9.8304
MHz
2.4576
MHz
9600
Provide external
clock at OSC1.
Forced
Monitor
V
DD
X
$FFFF
(blank)
1XXDisabled
9.8304
MHz
2.4576
MHz
9600
Provide external
clock at OSC1.
V
SS
X
$FFFF
(blank)
1XXDisabledX
3.2 MHz
(Trimmed)
9600
Internal clock is
active.
User X X
Not
$FFFF
X X X Enabled X X X
MON08
Function
[Pin No.]
V
TST
[6]
RST
[4]
—
COM
[8]
MOD0
[12]
MOD1
[10]
—
OSC1
[13]
——
1. PTA0 must have a pullup resistor to V
DD
in monitor mode.
2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus
frequency / 256 and baud rate using internal oscillator is bus frequency / 335.
3. External clock is a 9.8304 MHz oscillator on OSC1.
4. Lowering V
TST
once monitor mode is entered allows the clock source to be controlled by the OSCSC register.
5. X = don’t care
6. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector.
NC 1 2 GND
NC 3 4 RST
NC 5 6 IRQ
NC 7 8 PTA0
NC 9 10 PTA4
NC 11 12 PTA1
OSC1 13 14 NC
V
DD
15 16 NC