Datasheet

Registers
MC68HC908QB8 Data Sheet, Rev. 3
Freescale Semiconductor 171
15.8.1 SPI Control Register
The SPI control register:
• Enables SPI module interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
• Enables the SPI module
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables interrupt requests generated by the SPRF bit. The SPRF bit is set when a
byte transfers from the shift register to the receive data register.
1 = SPRF interrupt requests enabled
0 = SPRF interrupt requests disabled
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode operation.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See
Figure 15-4 and Figure 15-6.) To transmit data between SPI modules, the SPI modules must have
identical CPOL values.
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial clock and SPI data. (See
Figure 15-4 and Figure 15-6.) To transmit data between SPI modules, the SPI modules must have
identical CPHA values. When CPHA = 0, the SS
pin of the slave SPI module must be high between
bytes. (See Figure 15-12.)
SPWOM — SPI Wired-OR Mode Bit
This read/write bit configures pins SPSCK, MOSI, and MISO so that these pins become open-drain
outputs.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
SPE — SPI Enable
This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See 15.3.5
Resetting the SPI.)
1 = SPI module enabled
0 = SPI module disabled
Bit 7654321Bit 0
Read:
SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE
Write:
Reset:00101000
R
= Reserved
Figure 15-13. SPI Control Register (SPCR)