Datasheet

Serial Peripheral Interface (SPI) Module
MC68HC908QB8 Data Sheet, Rev. 3
170 Freescale Semiconductor
Figure 15-12. CPHA/SS Timing
When an SPI is configured as a slave, the SS
pin is always configured as an input. It cannot be used as
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can
still prevent the state of SS
from creating a MODF error. See 15.8.2 SPI Status and Control Register.
NOTE
A high on the SS
pin of a slave SPI puts the MISO pin in a high-impedance
state. The slave SPI ignores all incoming SPSCK clocks, even if it was
already in the middle of a transmission.
When an SPI is configured as a master, the SS
input can be used in conjunction with the MODF flag to
prevent multiple masters from driving MOSI and SPSCK. (See 15.3.6.2 Mode Fault Error.) For the state
of the SS
pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN
bit is 0 for an SPI master, the SS
pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. When MODFEN is 1, it is an input-only pin to the SPI regardless
of the state of the data direction register of the shared I/O port.
User software can read the state of the SS
pin by configuring the appropriate pin as an input and reading
the port data register. See Table 15-2.
15.8 Registers
The following registers allow the user to control and monitor SPI operation:
• SPI control register (SPCR)
• SPI status and control register (SPSCR)
• SPI data register (SPDR)
Table 15-2. SPI Configuration
SPE SPMSTR MODFEN SPI Configuration Function of SS Pin
0
X
(1)
1. X = Don’t care
X Not enabled
General-purpose I/O;
SS
ignored by SPI
1 0 X Slave Input-only to SPI
1 1 0 Master without MODF
General-purpose I/O;
SS
ignored by SPI
1 1 1 Master with MODF Input-only to SPI
BYTE 1 BYTE 3
MISO/MOSI
BYTE 2
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1