Datasheet

Interrupts
MC68HC908QB8 Data Sheet, Rev. 3
Freescale Semiconductor 167
In a slave SPI (MSTR = 0), MODF generates an SPI receiver/error interrupt request if the ERRIE bit is
set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort the SPI
transmission by clearing the SPE bit of the slave.
NOTE
A high on the SS
pin of a slave SPI puts the MISO pin in a high impedance
state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it was
already in the middle of a transmission.
To clear the MODF flag, read the SPSCR with the MODF bit set and then write to the SPCR register. This
entire clearing mechanism must occur with no MODF condition existing or else the flag is not cleared.
15.4 Interrupts
Four SPI status flags can be enabled to generate interrupt requests. See Table 15-1.
Reading the SPI status and control register with SPRF set and then reading the receive data register
clears SPRF. The clearing mechanism for the SPTE flag is requires only a write to the transmit data
register.
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter interrupt
requests, provided that the SPI is enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables SPRF to generate receiver interrupt requests,
regardless of the state of SPE. See Figure 15-11.
Figure 15-11. SPI Interrupt Request Generation
Table 15-1. SPI Interrupts
Flag Request
SPTE
Transmitter empty
SPI transmitter interrupt request
(SPTIE = 1, SPE = 1)
SPRF
Receiver full
SPI receiver interrupt request
(SPRIE = 1)
OVRF
Overflow
SPI receiver/error interrupt request
(ERRIE = 1)
MODF
Mode fault
SPI receiver/error interrupt request
(ERRIE = 1)
SPTE SPTIE
SPRFSPRIE
SPE
INTERRUPT REQUEST
INTERRUPT REQUEST
SPI TRANSMITTER
SPI RECEIVER/ERROR
ERRIE
MODF
OVRF