Datasheet

Serial Peripheral Interface (SPI) Module
MC68HC908QB8 Data Sheet, Rev. 3
162 Freescale Semiconductor
Figure 15-7. Transmission Start Delay (Master)
WRITE
TO SPDR
INITIATION DELAY
BUS
MOSI
SPSCK
CPHA = 1
SPSCK
CPHA = 0
SPSCK CYCLE
NUMBER
MSB BIT 6
12
CLOCK
WRITE
TO SPDR
EARLIEST
LATEST
SPSCK = BUS CLOCK ÷ 2;
EARLIEST LATEST
2 POSSIBLE START POINTS
SPSCK = BUS CLOCK ÷ 8;
8 POSSIBLE START POINTS
EARLIEST LATESTSPSCK = BUS CLOCK ÷ 32;
32 POSSIBLE START POINTS
EARLIEST LATESTSPSCK = BUS CLOCK ÷ 128;
128 POSSIBLE START POINTS
WRITE
TO SPDR
WRITE
TO SPDR
WRITE
TO SPDR
BUS
CLOCK
BIT 5
3
BUS
CLOCK
BUS
CLOCK
BUS
CLOCK
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN