Datasheet

System Integration Module (SIM)
MC68HC908QB8 Data Sheet, Rev. 3
148 Freescale Semiconductor
14.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
NOTE
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
14.6.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 14-3 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 14-3. Interrupt Sources
Priority Source Flag
Mask
(1)
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.
INT
Register
Flag
Vector
Address
Highest
Lowest
Reset — — — $FFFE–$FFFF
SWI instruction — — — $FFFC–$FFFD
IRQ
pin IRQF IMASK IF1 $FFFA–$FFFB
Timer channel 0 interrupt CH0F CH0IE IF3 $FFF6–$FFF7
Timer channel 1 interrupt CH1F CH1IE IF4 $FFF4–$FFF5
Timer overflow interrupt TOF TOIE IF5 $FFF2–$FFF3
TIM channel 2 vector CH2F CH2IE IF6 $FFF0–$FFF1
TIM channel 3 vector CH3F CH3IE IF7 $FFEE–$FFEF
ESCI error vector
OR, HF,
FE, PE
ORIE, NEIE,
FEIE, PEIE
IF9 $FFEA–$FFEB
ESCI receive vector SCRF SCRIE IF10 $FFE8–$FFE9
ESCI transmit vector SCTE, TC SCTIE, TCIE IF11 $FFE6–$FFE7
SPI receive
SPRF,
OVRF,
MODF
SPRIE, ERRIE IF12 $FFE4–$FFE5
SPI transmit SPTE SPTIE IF13 $FFE2–$FFE3
Keyboard interrupt KEYF IMASKK IF14 $FFE0–$FFE1
ADC conversion complete interrupt COCO AIEN IF15 $FFDE–$FFDF