Datasheet

System Integration Module (SIM)
MC68HC908QB8 Data Sheet, Rev. 3
142 Freescale Semiconductor
14.4.2 Active Resets from Internal Sources
The RST pin is initially setup as a general-purpose input after a POR. Setting the RSTEN bit in the
CONFIG2 register enables the pin for the reset function. This section assumes the RSTEN bit is set when
describing activity on the RST
pin.
NOTE
For POR and LVI resets, the SIM cycles through 4096 BUSCLKX4 cycles.
The internal reset signal then follows the sequence from the falling edge of
RST
shown in Figure 14-4.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
All internal reset sources actively pull the RST
pin low for 32 BUSCLKX4 cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles
(see Figure 14-4). An internal reset can be caused by an illegal address, illegal opcode, COP time out,
LVI, or POR (see Figure 14-5).
Figure 14-4. Internal Reset Timing
Figure 14-5. Sources of Internal Reset
Table 14-2. Reset Recovery Timing
Reset Recovery Type Actual Number of Cycles
POR/LVI 4163 (4096 + 64 + 3)
All others 67 (64 + 3)
IRST
RST
RST PULLED LOW BY MCU
ADDRESS
32 CYCLES 32 CYCLES
VECTOR HIGH
BUSCLKX4
BUS
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
LVI
INTERNAL RESET