Datasheet

System Integration Module (SIM)
MC68HC908QB8 Data Sheet, Rev. 3
140 Freescale Semiconductor
Figure 14-1. SIM Block Diagram
14.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, BUSCLKX2, as shown in Figure 14-2.
Figure 14-2. SIM Clock Signals
STOP/WAIT
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
INTERRUPT CONTROL
AND PRIORITY DECODE
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
BUSCLKX2 (FROM OSCILLATOR)
INTERNAL CLOCKS
MASTER
RESET
CONTROL
RESET
PIN LOGIC
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
RESET
CONTROL
SIM
COUNTER
COP CLOCK
BUSCLKX4 (FROM OSCILLATOR)
÷2
LVI RESET (FROM LVI MODULE)
V
DD
INTERNAL
PULL-UP
FORCED MON MODE ENTRY (FROM MENRST MODULE)
÷ 2
BUS CLOCK
GENERATORS
SIM
SIM COUNTER
FROM
OSCILLATOR
FROM
OSCILLATOR
BUSCLKX2
BUSCLKX4