Datasheet

ESCI Arbiter
MC68HC908QB8 Data Sheet, Rev. 3
Freescale Semiconductor 135
13.9 ESCI Arbiter
The ESCI module comprises an arbiter module designed to support software for communication tasks as
bus arbitration, baud rate recovery and break time detection. The arbiter module consists of an 9-bit
counter with 1-bit overflow and control logic. The can control operation mode via the ESCI arbiter control
register (SCIACTL).
13.9.1 ESCI Arbiter Control Register
AM1 and AM0 — Arbiter Mode Select Bits
These read/write bits select the mode of the arbiter module as shown in Table 13-11.
ALOST — Arbitration Lost Flag
This read-only bit indicates loss of arbitration. Clear ALOST by writing a 0 to AM1.
ACLK — Arbiter Counter Clock Select Bit
This read/write bit selects the arbiter counter clock source.
1 = Arbiter counter is clocked with one half of the ESCI input clock generated by the ESCI prescaler
0 = Arbiter counter is clocked with the bus clock divided by four
NOTE
For ACLK = 1, the arbiter input clock is driven from the ESCI prescaler. The
prescaler can be clocked by either the bus clock or BUSCLKX4 depending
on the state of the ESCIBDSRC bit in configuration register.
AFIN— Arbiter Bit Time Measurement Finish Flag
This read-only bit indicates bit time measurement has finished. Clear AFIN by writing any value to
SCIACTL.
1 = Bit time measurement has finished
0 = Bit time measurement not yet finished
Bit 7654321Bit 0
Read:
AM1
ALOST
AM0 ACLK
AFIN ARUN AROVFL ARD8
Write:
Reset:00000000
= Unimplemented
Figure 13-18. ESCI Arbiter Control Register (SCIACTL)
Table 13-11. ESCI Arbiter Selectable Modes
AM[1:0] ESCI Arbiter Mode
0 0 Idle / counter reset
0 1 Bit time measurement
1 0 Bus arbitration
1 1 Reserved / do not use