Datasheet

Enhanced Serial Communications Interface (ESCI) Module
MC68HC908QB8 Data Sheet, Rev. 3
132 Freescale Semiconductor
PDS2–PDS0 — Prescaler Divisor Select Bits
These read/write bits select the prescaler divisor as shown in Table 13-8.
NOTE
The setting of ‘000’ will bypass not only this prescaler but also the prescaler
divisor fine adjust (PDFA). It is not recommended to bypass the prescaler
while ENSCI is set, because the switching is not glitch free.
PSSB4–PSSB0 — Clock Insertion Select Bits
These read/write bits select the number of clocks inserted in each 32 output cycle frame to achieve
more timing resolution on the average prescaler frequency as shown in Table 13-9.
Table 13-8. ESCI Prescaler Division Ratio
PDS[2:1:0] Prescaler Divisor (PD)
0 0 0 Bypass this prescaler
001 2
010 3
011 4
100 5
101 6
110 7
111 8
Table 13-9. ESCI Prescaler Divisor Fine Adjust
PSSB[4:3:2:1:0] Prescaler Divisor Fine Adjust (PDFA)
00000 0/32 = 0
00001 1/32 = 0.03125
00010 2/32 = 0.0625
00011 3/32 = 0.09375
0 0 1 0 0 4/32 = 0.125
00101 5/32 = 0.15625
00110 6/32 = 0.1875
00111 7/32 = 0.21875
0 1 0 0 0 8/32 = 0.25
01001 9/32 = 0.28125
0 1 0 1 0 10/32 = 0.3125
0 1 0 1 1 11/32 = 0.34375
0 1 1 0 0 12/32 = 0.375
0 1 1 0 1 13/32 = 0.40625
0 1 1 1 0 14/32 = 0.4375
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