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MC68HC908QB8 Data Sheet, Addendum 5/2012

Freescale Semiconductor 1

Addendum to MC68HC908QB8, rev. 3

This addendum introduces a change to this data sheet.

Chapter 17 Development Support, Section 17.3.2 Security

A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host

can bypass the security feature at monitor mode entry by sending eight security bytes that match the

bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.

NOTE

Do not leave locations $FFF6–$FFFD blank. For security reasons, program

locations $FFF6–$FFFD even if they are not used for vectors.

Changes to:

Chapter 17 Development Support, Section 17.3.2 Security

A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host

can bypass the security feature at monitor mode entry by sending eight security bytes that match the

bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.

NOTE

Do not leave locations $FFF6–$FFFD blank. For security reasons, program

locations $FFF6–$FFFD even if they are not used for vectors. An improved

security function denies monitor mode entry if five or more of the eight

security bytes are $00 (zero bytes).

Summary of content (232 pages)

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Addendum to MC68HC908QB8, rev. 3 This addendum introduces a change to this data sheet. Chapter 17 Development Support, Section 17.3.2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Do not leave locations $FFF6–$FFFD blank.
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MC68HC908QB8 MC68HC908QB4 MC68HC908QY8 Data Sheet M68HC08 Microcontrollers MC68HC908QB8 Rev. 3 04/2010 freescale.
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MC68HC908QB8 MC68HC908QB4 MC68HC908QY8 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005–2010.
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Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date Revision Level September, 2005 1 April, 2007 April, 2010 2 3 Page Number(s) Description Initial full release N/A Chapter 3 Analog-to-Digital Converter (ADC10) Module — Renamed ADCSC register to ADSCR to be consistent with development tools. 37 Figure 4-1.
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List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Chapter 3 Analog-to-Digital Converter (ADC10) Module . . . . . . . . . . . . . . . . . . . . . . . . . 37 Chapter 4 Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Chapters Chapter 15 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Chapter 16 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 Chapter 17 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Chapter 18 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents Chapter 1 General Description 1.1 1.2 1.3 1.4 1.5 1.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . .
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Table of Contents 3.3.4.2 Pin Leakage Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.3 Noise-Induced Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.4 Code Width and Quantization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.5 Linearity Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.4 6.5 6.6 6.6.1 6.6.2 6.7 6.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 8.5 8.5.1 8.5.2 8.6 8.7 8.7.1 8.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Module During Break Interrupts . . . . . . . . . . .
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Chapter 11 Oscillator Module (OSC) 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3.
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Table of Contents Enhanced Serial Communications Interface (ESCI) Module 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.
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14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 15.3.3.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.3.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.4 Queuing Transmission Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.5 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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16.8.2 16.8.3 16.8.4 16.8.5 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 18.13 18.14 18.15 18.16 18.17 ADC10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Interface Module Characteristics . . . . . . . . . . . . . . .
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Chapter 1 General Description 1.1 Introduction The MC68HC908QB8 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 0.4 Table 1-1.
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General Description • • • • • • • • • • • • • • On-chip random-access memory (RAM) Enhanced serial communications interface (ESCI) module Serial peripheral interface (SPI) module 4-channel, 16-bit timer interface (TIM) module 10-channel, 10-bit analog-to-digital converter (ADC) with internal bandgap reference channel (ADC10) Up to 13 bidirectional input/output (I/O) lines and one input only: – Six shared with KBI – Ten shared with ADC – Four shared with TIM – Two shared with ESCI – Four shared with SPI
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MCU Block Diagram 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908QB8.
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General Description 1.4 Pin Assignments The MC68HC908QB8, MC68HC908QB4, and MC68HC908QY8 are available in 16-pin packages. Figure 1-2 shows the pin assignment for these packages.
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Pin Functions Table 1-2.
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General Description Table 1-2.
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Chapter 2 Memory 2.1 Introduction The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1. 2.2 Unimplemented Memory Locations Executing code from an unimplemented location will cause an illegal address reset. In Figure 2-1, unimplemented locations are shaded. 2.3 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation.
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Memory $0000 ↓ $003F IDIRECT PAGE REGISTERS 64 BYTES $0040 ↓ $013F RAM 256 BYTES RESERVED 64 BYTES $0040 ↓ $007F $0140 ↓ $27FF UNIMPLEMENTED 9920 BYTES RAM 128 BYTES $0080 ↓ $00FF $2800 ↓ $2A1F AUXILIARY ROM 544 BYTES RESERVED 64 BYTES $0100 ↓ $013F $2A20 ↓ $2F7D UNIMPLEMENTED 1374 BYTES $2F7E ↓ $2FFF AUXILIARY ROM 130 BYTES $3000 ↓ $DDFF UNIMPLEMENTED 44,544 BYTES $DE00 ↓ $FDFF FLASH MEMORY 8192 BYTES RESERVED 4096 BYTES $DE00 ↓ $EDFF $FE00 ↓ $FE1F MISCELLANEOUS REGISTERS 32 BYTES
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Direct Page Registers Addr. $0000 $0001 $0002 ↓ $0003 $0004 $0005 $0006 ↓ $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 Register Name Port A Data Register Read: (PTA) Write: See page 104. Reset: Port B Data Register Read: (PTB) Write: See page 106.
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Memory Addr. $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0020 $0021 Register Name ESCI Status Register 2 Read: (SCS2) Write: See page 129. Reset: ESCI Data Register Read: (SCDR) Write: See page 129. Reset: ESCI Baud Rate Register Read: (SCBR) Write: See page 130. Reset: ESCI Prescaler Register Read: (SCPSC) Write: See page 131. Reset: ESCI Arbiter Control Read: Register (SCIACTL) Write: See page 135.
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Direct Page Registers Addr. $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B ↓ $002F $0030 $0031 $0032 $0033 $0034 $0035 Register Name TIM Counter Register Low Read: (TCNTL) Write: See page 185. Reset: TIM Counter Modulo Read: Register High (TMODH) Write: See page 185. Reset: TIM Counter Modulo Read: Register Low (TMODL) Write: See page 185. Reset: TIM Channel 0 Status and Read: Control Register (TSC0) Write: See page 186.
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Memory Addr. $0036 $0037 $0038 $0039 ↓ $003B $003C $003D $003E $003F $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 Register Name Bit 7 6 Read: Oscillator Status and OSCOPT1 OSCOPT0 Control Register (OSCSC) Write: See page 100. Reset: 0 0 5 4 3 2 1 Bit 0 ECGST ICFS1 ICFS0 ECFS1 ECFS0 ECGON 0 0 0 0 0 0 Reserved Oscillator Trim Register (OSCTRIM) See page 101.
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Direct Page Registers Addr.
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Memory Table 2-1.
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FLASH Memory (FLASH) 2.6 FLASH Memory (FLASH) The FLASH memory is intended primarily for program storage. In-circuit programming allows the operating program to be loaded into the FLASH memory after final assembly of the application product. It is possible to program the entire array through the single-wire monitor mode interface.
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Memory ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation unselected PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time.
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FLASH Memory (FLASH) 2.6.3 FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory to read as a 1: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH address(1) within the FLASH memory address range. 4. Wait for a time, tNVS. 5. Set the HVEN bit. 6. Wait for a time, tMErase. 7. Clear the ERASE and MASS bits.
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Memory 6. 7. 8. 9. 10. 11. 12. 13. Wait for a time, tPGS. Write data to the FLASH address being programmed(1). Wait for time, tPROG. Repeat step 7 and 8 until all desired bytes within the row are programmed. Clear the PGM bit (1). Wait for time, tNVH. Clear the HVEN bit. After time, tRCV, the memory can be accessed in read mode again. NOTE The COP register at location $FFFF should not be written between steps 5-12, when the HVEN bit is set.
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FLASH Memory (FLASH) Algorithm for Programming a Row (32 Bytes) of FLASH Memory 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED 4 WAIT FOR A TIME, tNVS 5 SET HVEN BIT 6 WAIT FOR A TIME, tPGS 7 WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED 8 WAIT FOR A TIME, tPROG 9 COMPLETED PROGRAMMING THIS ROW? Y N 10 11 12 NOTES: The time between each FLASH address change (step 7 to step 7 loop), or the time between
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Memory 2.6.6 FLASH Block Protect Register The FLASH block protect register is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting address of the protected range within the FLASH memory. Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Reset: Unaffected by reset. Initial value from factory is 1.
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Chapter 3 Analog-to-Digital Converter (ADC10) Module 3.1 Introduction This section describes the 10-bit successive approximation analog-to-digital converter (ADC10). The ADC10 module shares its pins with general-purpose input/output (I/O) port pins. See Figure 3-1 for port location of these shared pins. The ADC10 on this MCU uses VDD and VSS as its supply and reference pins. This MCU uses BUSCLKX4 as its alternate clock source for the ADC. This MCU does not have a hardware conversion trigger. 3.
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Analog-to-Digital Converter (ADC10) Module PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 DDRA PTA2/IRQ/KBI2/TCLK PTA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/SCK/AD4 PTB1/MOSI/AD5 PTB2/MISO/AD6 PTB3/SS/AD7 PTB4/RxD/AD8 PTB5/TxD/AD9 PTB6/TCH2 PTB7/TCH3 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE MC68HC908QB8 MC68HC908QB8 256 BYTES 8192 BYTES USER RAM USER FLASH 10-CHA
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Functional Description ADIV ADLPC ADLSMP MODE COMPLETE 2 ADCO COCO AIEN ADCH 1 ADCK MCU STOP CONTROL SEQUENCER ADHWT ADICLK ADCLK ADSCR ACLKEN ASYNC CLOCK GENERATOR ACLK CLOCK DIVIDE BUS CLOCK ••• ADVIN ABORT CONVERT TRANSFER AD0 SAMPLE INITIALIZE ALTERNATE CLOCK SOURCE SAR CONVERTER AIEN 1 COCO 2 INTERRUPT ADn VREFH VREFL DATA REGISTERS ADRH:ADRL Figure 3-2.
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Analog-to-Digital Converter (ADC10) Module Whichever clock is selected, its frequency must fall within the acceptable frequency range for ADCK. If the available clocks are too slow, the ADC10 will not perform according to specifications. If the available clocks are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the ADIV[1:0] bits and can be divide-by 1, 2, 4, or 8. 3.3.
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Functional Description When a conversion is aborted, the contents of the data registers, ADRH and ADRL, are not altered but continue to be the values transferred after the completion of the last successful conversion. In the case that the conversion was aborted by a reset, ADRH and ADRL return to their reset states. Upon reset or when a conversion is otherwise aborted, the ADC10 module will enter a low power, inactive state. In this state, all internal clocks and references are disabled.
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Analog-to-Digital Converter (ADC10) Module 3.3.4 Sources of Error Several sources of error exist for ADC conversions. These are discussed in the following sections. 3.3.4.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 15 kΩ and input capacitance of approximately 10 pF, sampling to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.
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Functional Description 3.3.4.4 Code Width and Quantization Error The ADC10 quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step ideally has the same height (1 code) and width. The width is defined as the delta between the transition points from one code to the next. The ideal code width for an N bit converter (in this case N can be 8 or 10), defined as 1LSB, is: 1LSB = (VREFH–VREFL) / 2N Because of this quantization, there is an inherent quantization error.
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Analog-to-Digital Converter (ADC10) Module 3.4 Interrupts When AIEN is set, the ADC10 is capable of generating a CPU interrupt after each conversion. A CPU interrupt is generated when the conversion completes (indicated by COCO being set). COCO will set at the end of a conversion regardless of the state of AIEN. 3.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 3.5.
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I/O Signals break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. 3.7 I/O Signals The ADC10 module shares its pins with general-purpose input/output (I/O) port pins. See Figure 3-1 for port location of these shared pins. The ADC10 on this MCU uses VDD and VSS as its supply and reference pins. This MCU does not have an external trigger source. 3.7.
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Analog-to-Digital Converter (ADC10) Module charging. If externally available, connect the VREFL pin to the same potential as VSSA at the single point ground location. 3.7.5 ADC10 Channel Pins (ADn) The ADC10 has multiple input channels. Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. 0.01 μF capacitors with good high-frequency characteristics are sufficient.
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Registers (with ACLKEN low), continuous conversions will cease and can be restarted only with a write to ADSCR. Any write to ADSCR with ADCO set and the ADCH bits not all 1s will abort the current conversion and begin continuous conversions. If the bus frequency is less than the ADCK frequency, precise sample time for continuous conversions cannot be guaranteed in short-sample mode (ADLSMP = 0).
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Analog-to-Digital Converter (ADC10) Module 3.8.2 ADC10 Result High Register (ADRH) This register holds the MSBs of the result and is updated each time a conversion completes. All other bits read as 0s. Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the result registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then the intermediate conversion result will be lost.
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Registers 3.8.4 ADC10 Clock Register (ADCLK) This register selects the clock frequency for the ADC10 and the modes of operation. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 ADLPC ADIV1 ADIV0 ADICLK MODE1 MODE0 ADLSMP ACLKEN 0 0 0 0 0 0 0 0 Figure 3-7. ADC10 Clock Register (ADCLK) ADLPC — ADC10 Low-Power Configuration Bit ADLPC controls the speed and power configuration of the successive approximation converter.
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Analog-to-Digital Converter (ADC10) Module ADLSMP — Long Sample Time Configuration This bit configures the sample time of the ADC10 to either 3.5 or 23.5 ADCK clock cycles. This adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall power consumption in continuous conversion mode if high conversion rates are not required. 1 = Long sample time (23.
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Chapter 4 Auto Wakeup Module (AWU) 4.1 Introduction This section describes the auto wakeup module (AWU). The AWU generates a periodic interrupt during stop mode to wake the part up without requiring an external signal. Figure 4-1 is a block diagram of the AWU.
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Auto Wakeup Module (AWU) 4.3 Functional Description The function of the auto wakeup logic is to generate periodic wakeup requests to bring the microcontroller unit (MCU) out of stop mode. The wakeup requests are treated as regular keyboard interrupt requests, with the difference that instead of a pin, the interrupt signal is generated by an internal logic. Entering stop mode will enable the auto wakeup generation logic.
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Low-Power Modes 4.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 4.5.1 Wait Mode The AWU module remains inactive in wait mode. 4.5.2 Stop Mode When the AWU module is enabled (AWUIE = 1 in the keyboard interrupt enable register) it is activated automatically upon entering stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode.
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Auto Wakeup Module (AWU) 4.6.2 Keyboard Status and Control Register The keyboard status and control register (KBSCR): • Flags keyboard/auto wakeup interrupt requests • Acknowledges keyboard/auto wakeup interrupt requests • Masks keyboard/auto wakeup interrupt requests Read: Bit 7 6 5 4 3 0 0 0 0 KEYF Write: Reset: 2 0 ACKK 0 0 0 0 0 0 1 Bit 0 IMASKK MODEK 0 0 = Unimplemented Figure 4-3.
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Registers AWUIE — Auto Wakeup Interrupt Enable Bit This read/write bit enables the auto wakeup interrupt input to latch interrupt requests. Reset clears AWUIE. 1 = Auto wakeup enabled as interrupt input 0 = Auto wakeup not enabled as interrupt input NOTE KBIE5–KBIE0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see 9.8.2 Keyboard Interrupt Enable Register (KBIER). 4.6.
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Auto Wakeup Module (AWU) COPRS (In Stop Mode) — Auto Wakeup Period Selection Bit, depends on OSCSTOPEN in CONFIG2 and bus clock source (BUSCLKX2). 1 = Auto wakeup short cycle = 512 × (INTRCOSC or BUSCLKX2) 0 = Auto wakeup long cycle = 16,384 × (INTRCOSC or BUSCLKX2) SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a 4096 BUSCLKX4 cycle delay.
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Chapter 5 Configuration Register (CONFIG) 5.1 Introduction This section describes the configuration registers (CONFIG1 and CONFIG2).
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Configuration Register (CONFIG) IRQPUD — IRQ Pin Pullup Control Bit 1 = Internal pullup is disconnected 0 = Internal pullup is connected between IRQ pin and VDD IRQEN — IRQ Pin Function Selection Bit 1 = Interrupt request function active in pin 0 = Interrupt request function inactive in pin ESCIBDSRC — ESCI Baud Rate Clock Source Bit ESCIBDSRC controls the clock source used for the ESCI. The setting of the bit affects the frequency at which the ESCI operates.
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Functional Description LVIRSTD — LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module. 1 = LVI module resets disabled 0 = LVI module resets enabled LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module. 1 = LVI module power disabled 0 = LVI module power enabled LVITRIP — LVI Trip Point Selection Bit LVITRIP selects the voltage operating mode of the LVI module.
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Configuration Register (CONFIG) MC68HC908QB8 Data Sheet, Rev.
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Chapter 6 Computer Operating Properly (COP) 6.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the configuration 1 (CONFIG1) register. 6.
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Computer Operating Properly (COP) The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 8176 or 262,128 BUSCLKX4 cycles; depending on the state of the COP rate select bit, COPRS, in configuration register 1. With a 262,128 BUSCLKX4 cycle overflow option, the internal 12.8-MHz oscillator gives a COP timeout period of 20.48 ms.
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Interrupts 6.3.7 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1 (CONFIG1). See Chapter 5 Configuration Register (CONFIG). 6.4 Interrupts The COP does not generate CPU interrupt requests. 6.5 Monitor Mode The COP is disabled in monitor mode when VTST is present on the IRQ pin. 6.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 6.6.
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Computer Operating Properly (COP) MC68HC908QB8 Data Sheet, Rev.
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Chapter 7 Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 7.
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Central Processor Unit (CPU) 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers 7.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
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CPU Registers 7.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
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Central Processor Unit (CPU) 7.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 7-6.
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Arithmetic/Logic Unit (ALU) Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.
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Central Processor Unit (CPU) 7.7 Instruction Set Summary Table 7-1 provides a summary of the M68HC08 instruction set.
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Instruction Set Summary Effect on CCR V H I N Z C BHS rel Branch if Higher or Same (Same as BCC) BIH rel BIL rel PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 (A) & (M) BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test BLE opr Branch if Less Than or Equal To (Signed Operands) Cycles Description Operand Operation Opcode Source Form Address Mode Table
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Central Processor Unit (CPU) CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP V H I N Z C Clear Compare A with M COM opr COMA COMX COM opr,X COM ,X COM opr,SP Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP Decrement DIV Divide INC opr INCA
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Instruction Set Summary JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine LDHX #opr LDHX opr Load H:X from M 2 3 4 3 2 PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Unconditional Address DIR EXT – – – – – – IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff 4 5 6 5 4 A ← (M) IMM DIR EXT IX2 0 – – – IX1 IX SP1 SP2 A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ii jj dd 3 4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 H:
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Central Processor Unit (CPU) V H I N Z C Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1.
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Opcode Map SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte – – 1 – – – INH 83 9 CCR ← (A) INH 84 2 X ← (A) – – – – – – INH 97 1 A ← (CCR) – – – – – – INH 85 (A) – $00 or (X) – $00 or (M) – $00 DIR INH INH 0 – – – IX1 IX SP1 H:X ← (SP) + 1 – – – – – – INH 95 2 A ← (X) – – – – – – INH
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MSB Branch REL DIR INH 3 4 0 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BR
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Chapter 8 External Interrupt (IRQ) 8.1 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. IRQ functionality is enabled by setting configuration register 2 (CONFIG2) IRQEN bit accordingly. A zero disables the IRQ function and IRQ will assume the other shared functionalities. A one enables the IRQ function. See Chapter 5 Configuration Register (CONFIG) for more information on enabling the IRQ pin. The IRQ pin shares its pin with general-purpose input/output (I/O) port pins.
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External Interrupt (IRQ) PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 DDRA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU AUTO WAKEUP MODULE DDRB PTB PTB0/SCK/AD4 PTB1/MOSI/AD5 PTB2/MISO/AD6 PTB3/SS/AD7 PTB4/RxD/AD8 PTB5/TxD/AD9 PTB6/TCH2 PTB7/TCH3 EXTERNAL INTERRUPT MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE MC68HC908QB8 MC68HC908QB8 256 BYTES 8192 BYTES USER RAM USER FLASH 10-CHANNEL 10-BIT ADC ENHA
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Functional Description RESET ACK TO CPU FOR BIL/BIH INSTRUCTIONS INTERNAL ADDRESS BUS IRQ VECTOR FETCH DECODER VDD INTERNAL PULLUP DEVICE VDD IRQF D CLR Q CK IRQ IRQ LATCH SYNCHRONIZER IRQ INTERRUPT REQUEST IMASK MODE HIGH VOLTAGE DETECT TO MODE SELECT LOGIC Figure 8-2. IRQ Module Block Diagram 8.3.1 MODE = 1 If the MODE bit is set, the IRQ pin is both falling edge sensitive and low level sensitive.
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External Interrupt (IRQ) 8.4 Interrupts The following IRQ source can generate interrupt requests: • Interrupt flag (IRQF) — The IRQF bit is set when the IRQ pin is asserted based on the IRQ mode.. The IRQ interrupt mask bit, IMASK, is used to enable or disable IRQ interrupt requests. 8.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 8.5.1 Wait Mode The IRQ module remains active in wait mode.
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Registers 8.8 Registers The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: • Shows the state of the IRQ flag • Clears the IRQ latch • Masks the IRQ interrupt request • Controls triggering sensitivity of the IRQ interrupt pin Read: Bit 7 6 5 4 3 2 0 0 0 0 IRQF 0 Write: Reset: ACK 0 0 0 0 0 1 Bit 0 IMASK MODE 0 0 0 = Unimplemented Figure 8-3.
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External Interrupt (IRQ) MC68HC908QB8 Data Sheet, Rev.
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Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction The keyboard interrupt module (KBI) provides independently maskable external interrupts. The KBI shares its pins with general-purpose input/output (I/O) port pins. See Figure 9-1 for port location of these shared pins. 9.
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Keyboard Interrupt Module (KBI) PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 DDRA PTA2/IRQ/KBI2/TCLK PTA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/SCK/AD4 PTB1/MOSI/AD5 PTB2/MISO/AD6 PTB3/SS/AD7 PTB4/RxD/AD8 PTB5/TxD/AD9 PTB6/TCH2 PTB7/TCH3 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE MC68HC908QB8 MC68HC908QB8 256 BYTES 8192 BYTES USER RAM USER FLASH 10-CHANNEL 10-BIT
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Functional Description INTERNAL BUS VECTOR FETCH DECODER ACKK RESET 1 KBI0 0 S VDD KBIE0 TO PULLUP/ PULLDOWN ENABLE KBIP0 KEYF D CLR Q CK 1 KBIx 0 KBI LATCH S IMASKK KBIEx TO PULLUP/ PULLDOWN ENABLE KBIPx SYNCHRONIZER MODEK KEYBOARD INTERRUPT REQUEST AWUIREQ (SEE Figure 4-1) Figure 9-2. Keyboard Interrupt Block Diagram • Vector fetch or software clear. A KBI vector fetch generates an interrupt acknowledge signal to clear the KBI latch.
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Keyboard Interrupt Module (KBI) 9.3.2 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pullup or pulldown device to pull the pin to its deasserted level. Therefore a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting IMASKK in KBSCR. 2. Enable the KBI polarity by setting the appropriate KBIPx bits in KBIPR. 3.
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I/O Signals 9.7 I/O Signals The KBI module can share its pins with the general-purpose I/O pins. See Figure 9-1 for the port pins that are shared. 9.7.1 KBI Input Pins (KBIx:KBI0) Each KBI pin is independently programmable as an external interrupt source. KBI pin polarity can be controlled independently. Each KBI pin when enabled will automatically configure the appropriate pullup/pulldown device based on polarity. 9.
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Keyboard Interrupt Module (KBI) 9.8.2 Keyboard Interrupt Enable Register (KBIER) KBIER enables or disables each keyboard interrupt pin. Bit 7 Read: 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 = Unimplemented Figure 9-4. Keyboard Interrupt Enable Register (KBIER) KBIE5–KBIE0 — Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch KBI interrupt requests.
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Chapter 10 Low-Voltage Inhibit (LVI) 10.1 Introduction The low-voltage inhibit (LVI) module is provided as a system protection mechanism to prevent the MCU from operating below a certain operating supply voltage level. The module has several configuration options to allow functionality to be tailored to different system level demands. The configuration registers (see Chapter 5 Configuration Register (CONFIG)) contain control bits for this module. 10.
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Low-Voltage Inhibit (LVI) The LVI module contains a bandgap reference circuit and comparator. When the LVITRIP bit is cleared, the default state at power-on reset, VTRIPF is configured for the lower VDD operating range. The actual trip points are specified in 18.5 5-V DC Electrical Characteristics and 18.8 3-V DC Electrical Characteristics.
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LVI Interrupts 10.4 LVI Interrupts The LVI module does not generate interrupt requests. 10.5 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. 10.5.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 10.5.
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Low-Voltage Inhibit (LVI) MC68HC908QB8 Data Sheet, Rev.
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Chapter 11 Oscillator Module (OSC) 11.1 Introduction The oscillator (OSC) module is used to provide a stable clock source for the MCU system and bus. The OSC shares its pins with general-purpose input/output (I/O) port pins. See Figure 11-1 for port location of these shared pins. The OSC2EN bit is located in the port A pull enable register (PTAPUEN) on this MCU. See Chapter 12 Input/Output Ports (PORTS) for information on PTAPUEN register. 11.
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Oscillator Module (OSC) PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 DDRA PTA2/IRQ/KBI2/TCLK PTA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/SCK/AD4 PTB1/MOSI/AD5 PTB2/MISO/AD6 PTB3/SS/AD7 PTB4/RxD/AD8 PTB5/TxD/AD9 PTB6/TCH2 PTB7/TCH3 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE MC68HC908QB8 256 BYTES 8192 BYTES USER RAM USER FLASH 10-CHANNEL 10-BIT ADC ENHANCED SERIAL CO
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Functional Description 11.3.1 Internal Signal Definitions The following signals and clocks are used in the functional description and figures of the OSC module. 11.3.1.1 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the system integration module (SIM) and disables the XTAL oscillator circuit, the RC oscillator, or the internal oscillator in stop mode. OSCENINSTOP in the configuration register can be used to override this signal. 11.3.1.
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Oscillator Module (OSC) Figure 11-3 shows how BUSCLKX4 is derived from INTCLK and OSC2 can output BUSCLKX4 by setting OSC2EN. 11.3.2.1 Internal Oscillator Trimming OSCTRIM allows a clock period adjustment of +127 and –128 steps. Increasing the OSCTRIM value increases the clock period, which decreases the clock frequency. Trimming allows the internal clock frequency to be fine tuned to the target frequency.
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Functional Description 11.3.4 XTAL Oscillator The XTAL oscillator circuit is designed for use with an external crystal or ceramic resonator to provide an accurate clock source. In this configuration, the OSC2 pin is dedicated to the external crystal circuit. The OSC2EN bit has no effect when this clock mode is selected. In its typical configuration, the XTAL oscillator is connected in a Pierce oscillator configuration, as shown in Figure 11-2.
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Oscillator Module (OSC) 11.3.5 RC Oscillator The RC oscillator circuit is designed for use with an external resistor (REXT) to provide a clock source with a tolerance within 25% of the expected frequency. See Figure 11-3. The capacitor (C) for the RC oscillator is internal to the MCU. The REXT value must have a tolerance of 1% or less to minimize its effect on the frequency. In this configuration, the OSC2 pin can be used as general-purpose input/output (I/O) port pins or other alternative pin function.
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OSC During Break Interrupts 11.6 OSC During Break Interrupts There are no status flags associated with the OSC module. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See BFCR in the SIM section of this data sheet. To allow software to clear status bits during a break interrupt, write a 1 to BCFE.
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Oscillator Module (OSC) 11.8 Registers The oscillator module contains two registers: • Oscillator status and control register (OSCSC) • Oscillator trim register (OSCTRIM) 11.8.1 Oscillator Status and Control Register The oscillator status and control register (OSCSC) contains the bits for switching between internal and external clock sources. If the application uses an external crystal, bits in this register are used to select the crystal oscillator amplifier necessary for the desired crystal.
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Registers ECFS1:ECFS0 — External Crystal Frequency Select Bits These read/write bits enable the specific amplifier for the crystal frequency range. Refer to oscillator characteristics table in the Electricals section for information on maximum external clock frequency versus supply voltage.
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Oscillator Module (OSC) MC68HC908QB8 Data Sheet, Rev.
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Chapter 12 Input/Output Ports (PORTS) 12.1 Introduction The MC68HC908QB8, MC68HC908QB4 and MC68HC908QY8 have thirteen bidirectional pins and one input only pin. NOTE Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. 12.
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Input/Output Ports (PORTS) 12.2.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the six port A pins. Bit 7 Read: Write: R 6 AWUL 5 4 3 PTA5 PTA4 PTA3 Reset: 2 PTA2 1 Bit 0 PTA1 PTA0 Unaffected by reset = Unimplemented Figure 12-1. Port A Data Register (PTA) PTA[5:0] — Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A.
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Port A READ DDRA PTAPUEx INTERNAL DATA BUS WRITE DDRA DDRAx RESET WRITE PTA PULLUP PTAx PTAx READ PTA Figure 12-3. Port A I/O Circuit NOTE Figure 12-3 does not apply to PTA2 When DDRAx is a 1, reading PTA reads the PTAx data latch. When DDRAx is a 0, reading PTA reads the logic level on the PTAx pin. The data latch can always be written, regardless of the state of its data direction bit. 12.2.
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Input/Output Ports (PORTS) 12.2.4 Port A Summary Table The following table summarizes the operation of the port A pins when used as a general-purpose input/output pins. Table 12-1. Port A Pin Functions PTAPUE Bit DDRA Bit PTA Bit I/O Pin Mode Accesses to DDRA Accesses to PTA Read/Write Read Write 1 0 X(1) Input, VDD(2) DDRA5–DDRA0 Pin PTA5–PTA0(3) 0 0 X Input, Hi-Z(4) DDRA5–DDRA0 Pin PTA5–PTA0(3) X 1 X Output DDRA5–DDRA0 PTA5–PTA0 PTA5–PTA0(5) 1. X = don’t care 2.
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Port B 12.3.2 Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 Figure 12-6.
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Input/Output Ports (PORTS) 12.3.3 Port B Input Pullup Enable Register The port B input pullup enable register (PTBPUE) contains a software configurable pullup device for each of the eight port B pins. Each bit is individually configurable and requires the corresponding data direction register, DDRBx, be configured as input. Each pullup device is automatically and dynamically disabled when its corresponding DDRBx bit is configured as output.
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Chapter 13 Enhanced Serial Communications Interface (ESCI) Module 13.1 Introduction The enhanced serial communications interface (ESCI) module allows asynchronous communications with peripheral devices and other microcontroller units (MCU). The ESCI module shares its pins with general-purpose input/output (I/O) port pins. See Figure 13-1 for port location of these shared pins. The ESCI baud rate clock source is controlled by a bit (ESCIBDSRC) located in the configuration register. 13.
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Enhanced Serial Communications Interface (ESCI) Module PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 DDRA PTA2/IRQ/KBI2/TCLK PTA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/SCK/AD4 PTB1/MOSI/AD5 PTB2/MISO/AD6 PTB3/SS/AD7 PTB4/RxD/AD8 PTB5/TxD/AD9 PTB6/TCH2 PTB7/TCH3 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE MC68HC908QB8 MC68HC908QB8 256 BYTES 8192 BYTES USER RAM USER F
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Functional Description 13.3 Functional Description Figure 13-2 shows the structure of the ESCI module. The ESCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the ESCI operate independently, although they use the same baud rate generator.
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Enhanced Serial Communications Interface (ESCI) Module 13.3.1 Data Format The SCI uses the standard mark/space non-return-to-zero (NRZ) format illustrated in Figure 13-3. START BIT START BIT PARITY OR DATA BIT 8-BIT DATA FORMAT (BIT M IN SCC1 CLEAR) BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 STOP BIT PARITY OR DATA BIT 9-BIT DATA FORMAT (BIT M IN SCC1 SET) BIT 0 NEXT START BIT BIT 6 BIT 7 BIT 8 NEXT START BIT STOP BIT Figure 13-3.
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Functional Description 13.3.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in ESCI control register 3 (SCC3) is the ninth bit (bit 8). 13.3.2.2 Character Transmission During an ESCI transmission, the transmit shift register shifts a character out to the TxD pin.
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Enhanced Serial Communications Interface (ESCI) Module Receiving a break character has these effects on ESCI registers: • Sets the framing error bit (FE) in SCS1 • Sets the ESCI receiver full bit (SCRF) in SCS1 • Clears the ESCI data register (SCDR) • Clears the R8 bit in SCC3 • Sets the break flag bit (BKF) in SCS2 • May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits 13.3.2.
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Functional Description INTERNAL BUS SCP1 SCR1 SCP0 SCR0 DATA RECOVERY ALL ZEROS PDS2 RPF PDS1 PDS0 PSSB4 PSSB3 PSSB2 H 8 7 6 5 M WAKE ILTY PSSB1 PEN PSSB0 PTY RECEIVER INTERRUPT REQUEST 11-BIT RECEIVE SHIFT REGISTER STOP ÷ 16 RxD BKF BUSCLKX4 OR BUS CLOCK BAUD DIVIDER ALL ONES PRESCALER PRESCALER ÷4 ESCI DATA REGISTER 4 3 SCRF WAKEUP LOGIC PARITY CHECKING IDLE ILIE SCRF SCRIE OR ORIE NF NEIE ERROR INTERRUPT REQUEST START SCR2 2 1 0 L MSB LINR FE FEIE PE PEIE RWU
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Enhanced Serial Communications Interface (ESCI) Module 13.3.3.3 Data Sampling The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate.
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Functional Description Table 13-2. Data Bit Recovery RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 NOTE The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit.
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Enhanced Serial Communications Interface (ESCI) Module Slow Data Tolerance Figure 13-7 shows how much a slow received character can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. MSB STOP RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RECEIVER RT CLOCK DATA SAMPLES Figure 13-7.
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Interrupts For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 13-8, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times × 16 RT cycles = 160 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is 154 – 160 -------------------------- × 100 = 3.90%.
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Enhanced Serial Communications Interface (ESCI) Module 13.4.1 Transmitter Interrupts These conditions can generate interrupt requests from the ESCI transmitter: • ESCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register. SCTE can generate a transmitter interrupt request. Setting the ESCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate transmitter interrupt requests.
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ESCI During Break Interrupts 13.5.2 Stop Mode The ESCI module is inactive in stop mode. The STOP instruction does not affect ESCI register states. ESCI module operation resumes after the MCU exits stop mode. Because the internal clock is inactive during stop mode, entering stop mode during an ESCI transmission or reception results in invalid data. 13.6 ESCI During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state.
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Enhanced Serial Communications Interface (ESCI) Module 13.8.1 ESCI Control Register 1 ESCI control register 1 (SCC1): • Enables loop mode operation • Enables the ESCI • Controls output polarity • Controls character length • Controls ESCI wakeup method • Controls idle character detection • Enables parity function • Controls parity type Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY 0 0 0 0 0 0 0 0 Figure 13-9.
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Registers Table 13-4.
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Enhanced Serial Communications Interface (ESCI) Module • • • Enables the receiver Enables ESCI wakeup Transmits ESCI break characters Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 SCTIE TCIE SCRIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Figure 13-10. ESCI Control Register 2 (SCC2) SCTIE — ESCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate ESCI transmitter interrupt requests.
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Registers NOTE Writing to the RE bit is not allowed when the enable ESCI bit (ENSCI) is clear. ENSCI is in ESCI control register 1. RWU — Receiver Wakeup Bit This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the RWU bit.
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Enhanced Serial Communications Interface (ESCI) Module ORIE — Receiver Overrun Interrupt Enable Bit This read/write bit enables ESCI error interrupt requests generated by the receiver overrun bit, OR. 1 = ESCI error interrupt requests from OR bit enabled 0 = ESCI error interrupt requests from OR bit disabled NEIE — Receiver Noise Error Interrupt Enable Bit This read/write bit enables ESCI error interrupt requests generated by the noise error bit, NE.
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Registers TC — Transmission Complete Bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates an ESCI transmitter interrupt request if the TCIE bit in SCC2 is also set. TC is cleared automatically when data, preamble, or break is queued and ready to be sent. There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting.
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Enhanced Serial Communications Interface (ESCI) Module BYTE 1 BYTE 2 BYTE 3 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 NORMAL FLAG CLEARING SEQUENCE BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1 READ SCDR BYTE 2 READ SCDR BYTE 3 BYTE 1 BYTE 2 BYTE 3 SCRF = 0 OR = 0 SCRF = 1 OR = 1 SCRF = 0 OR = 1 SCRF = 1 SCRF = 1 OR = 1 DELAYED FLAG CLEARING SEQUENCE BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 1 RE
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Registers 13.8.5 ESCI Status Register 2 ESCI status register 2 (SCS2) contains flags to signal these conditions: • Break character detected • Reception in progress Read: Write: Reset: Bit 7 0 0 6 0 5 0 4 0 3 0 2 0 1 BKF Bit 0 RPF 0 0 = Unimplemented 0 0 0 0 0 Figure 13-14. ESCI Status Register 2 (SCS2) BKF — Break Flag Bit This clearable, read-only bit is set when the ESCI detects a break character on the RxD pin. In SCS1, the FE and SCRF bits are also set.
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Enhanced Serial Communications Interface (ESCI) Module 13.8.7 ESCI Baud Rate Register The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for both the receiver and the transmitter. NOTE There are two prescalers available to adjust the baud rate — one in the ESCI baud rate register and one in the ESCI prescaler register.
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Registers SCP1 and SCP0 — ESCI Baud Rate Register Prescaler Bits These read/write bits select the baud rate register prescaler divisor as shown in Table 13-6. Table 13-6. ESCI Baud Rate Prescaling SCP[1:0] Baud Rate Register Prescaler Divisor (BPD) 0 0 1 0 1 3 1 0 4 1 1 13 SCR2–SCR0 — ESCI Baud Rate Select Bits These read/write bits select the ESCI baud rate divisor as shown in Table 13-7. Reset clears SCR2–SCR0. Table 13-7.
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Enhanced Serial Communications Interface (ESCI) Module PDS2–PDS0 — Prescaler Divisor Select Bits These read/write bits select the prescaler divisor as shown in Table 13-8. NOTE The setting of ‘000’ will bypass not only this prescaler but also the prescaler divisor fine adjust (PDFA). It is not recommended to bypass the prescaler while ENSCI is set, because the switching is not glitch free. Table 13-8.
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Registers Table 13-9. ESCI Prescaler Divisor Fine Adjust (Continued) PSSB[4:3:2:1:0] Prescaler Divisor Fine Adjust (PDFA) 0 1 1 1 1 15/32 = 0.46875 1 0 0 0 0 16/32 = 0.5 1 0 0 0 1 17/32 = 0.53125 1 0 0 1 0 18/32 = 0.5625 1 0 0 1 1 19/32 = 0.59375 1 0 1 0 0 20/32 = 0.625 1 0 1 0 1 21/32 = 0.65625 1 0 1 1 0 22/32 = 0.6875 1 0 1 1 1 23/32 = 0.71875 1 1 0 0 0 24/32 = 0.75 1 1 0 0 1 25/32 = 0.78125 1 1 0 1 0 26/32 = 0.8125 1 1 0 1 1 27/32 = 0.84375 1 1 1 0 0 28/32 = 0.
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Enhanced Serial Communications Interface (ESCI) Module Table 13-10. ESCI Baud Rate Selection Examples PDS[2:1:0] PSSB[4:3:2:1:0] SCP[1:0] Prescaler Divisor (BPD) SCR[2:1:0] Baud Rate Divisor (BD) 0 0 0 X X X X X 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 1 9600 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 9562.65 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 9525.58 1 1 1 1 1 1 1 1 0 0 1 0 0 0 1 8563.
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ESCI Arbiter 13.9 ESCI Arbiter The ESCI module comprises an arbiter module designed to support software for communication tasks as bus arbitration, baud rate recovery and break time detection. The arbiter module consists of an 9-bit counter with 1-bit overflow and control logic. The can control operation mode via the ESCI arbiter control register (SCIACTL). 13.9.
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Enhanced Serial Communications Interface (ESCI) Module ARUN— Arbiter Counter Running Flag This read-only bit indicates the arbiter counter is running. 1 = Arbiter counter running 0 = Arbiter counter stopped AROVFL— Arbiter Counter Overflow Bit This read-only bit indicates an arbiter counter overflow. Clear AROVFL by writing any value to SCIACTL. Writing 0s to AM1 and AM0 resets the counter keeps it in this idle state.
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ESCI Arbiter MEASURED TIME READ RESULT OUT OF SCIADAT COUNTER STOPS, AFIN = 1 COUNTER STARTS, ARUN = 1 WRITE SCIACTL WITH $20 RXD Figure 13-20. Bit Time Measurement with ACLK = 0 MEASURED TIME READ RESULT OUT OF SCIADAT COUNTER STOPS, AFIN = 1 WRITE SCIACTL WITH $30 COUNTER STARTS, ARUN = 1 RXD Figure 13-21. Bit Time Measurement with ACLK = 1, Scenario A MEASURED TIME READ RESULT OUT OF SCIADAT COUNTER STOPS, AFIN = 1 COUNTER STARTS, ARUN = 1 WRITE SCIACTL WITH $30 RXD Figure 13-22.
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Enhanced Serial Communications Interface (ESCI) Module 13.9.4 Arbitration Mode If AM[1:0] is set to 10, the arbiter module operates in arbitration mode. On every rising edge of SCI_TxD (output of the transmit shift register, see Figure 13-2), the counter is started. When the counter reaches $38 (ACLK = 0) or $08 (ACLK = 1), RxD is statically sensed. If in this case, RxD is sensed low (for example, another bus is driving the bus dominant) ALOST is set.
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Chapter 14 System Integration Module (SIM) 14.1 Introduction This section describes the system integration module (SIM), which supports up to 24 external and/or internal interrupts. Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in Figure 14-1. The SIM is a system state controller that coordinates CPU and exception timing.
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System Integration Module (SIM) MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO OSCILLATOR) SIM COUNTER COP CLOCK BUSCLKX4 (FROM OSCILLATOR) BUSCLKX2 (FROM OSCILLATOR) ÷2 VDD INTERNAL PULL-UP RESET PIN LOGIC CLOCK CONTROL INTERNAL CLOCKS CLOCK GENERATORS POR CONTROL ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) MASTER RESET CONTROL RESET PIN CONTROL LVI RESET (FROM LVI MODULE) SIM RESET STATUS
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Reset and System Initialization 14.3.1 Bus Timing In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4) divided by four. 14.3.2 Clock Start-Up from POR When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 BUSCLKX4 cycle POR time out has completed. The IBUS clocks start upon completion of the time out. 14.3.
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System Integration Module (SIM) 14.4.2 Active Resets from Internal Sources The RST pin is initially setup as a general-purpose input after a POR. Setting the RSTEN bit in the CONFIG2 register enables the pin for the reset function. This section assumes the RSTEN bit is set when describing activity on the RST pin. NOTE For POR and LVI resets, the SIM cycles through 4096 BUSCLKX4 cycles. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 14-4.
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Reset and System Initialization 14.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4 cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power on, the following events occur: • A POR pulse is generated. • The internal reset signal is asserted.
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System Integration Module (SIM) If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 14.4.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset.
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Exception Control 14.6 Exception Control Normal sequential program execution can be changed in three different ways: 1. Interrupts a. Maskable hardware CPU interrupts b. Non-maskable software interrupt instruction (SWI) 2. Reset 3. Break interrupts 14.6.1 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 14-7 flow charts the handling of system interrupts.
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System Integration Module (SIM) FROM RESET BREAK INTERRUPT? I BIT SET? YES NO YES I BIT SET? NO IRQ INTERRUPT? YES NO TIMER INTERRUPT? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR (AS MANY INTERRUPTS AS EXIST ON CHIP) FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 14-7. Interrupt Processing MC68HC908QB8 Data Sheet, Rev.
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Exception Control MODULE INTERRUPT I BIT ADDRESS BUS DUMMY DATA BUS SP DUMMY SP – 1 SP – 2 PC – 1[7:0] PC – 1[15:8] SP – 3 X SP – 4 A VECT H CCR VECT L V DATA H START ADDR V DATA L OPCODE R/W Figure 14-8. Interrupt Entry MODULE INTERRUPT I BIT ADDRESS BUS SP – 4 DATA BUS SP – 3 CCR SP – 2 A SP – 1 X SP PC PC + 1 PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND R/W Figure 14-9.
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System Integration Module (SIM) 14.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does. 14.6.2 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources.
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Exception Control 14.6.2.1 Interrupt Status Register 1 Bit 7 6 5 4 3 2 Read: IF6 IF5 IF4 Write: R R R Reset: 0 0 0 R = Reserved 1 Bit 0 IF3 0 IF1 0 0 R R R R R 0 0 0 0 0 Figure 14-11. Interrupt Status Register 1 (INT1) IF1 and IF3–IF6 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 14-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0, 1, and 3— Always read 0 14.6.2.
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System Integration Module (SIM) 14.6.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 14.6.4 Break Interrupts The break module can stop normal program flow at a software programmable break point by asserting its break interrupt output. (See Chapter 17 Development Support.) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state.
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Low-Power Modes In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset (or break in emulation mode). A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the break status register (BSR).
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System Integration Module (SIM) The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 14-17 shows stop mode entry timing and Figure 14-18 shows the stop mode recovery time from interrupt or break NOTE To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.
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SIM Registers POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN — External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP — Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit (illegal attempt to fetch an opcode from an unimplemented address) 1 = Last reset
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System Integration Module (SIM) MC68HC908QB8 Data Sheet, Rev.
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Chapter 15 Serial Peripheral Interface (SPI) Module 15.1 Introduction This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices. The SPI shares its pins with general-purpose input/output (I/O) port pins. See Figure 15-1 for port location of these shared pins. 15.
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Serial Peripheral Interface (SPI) Module PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 DDRA PTA2/IRQ/KBI2/TCLK PTA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/SCK/AD4 PTB1/MOSI/AD5 PTB2/MISO/AD6 PTB3/SS/AD7 PTB4/RxD/AD8 PTB5/TxD/AD9 PTB6/TCH2 PTB7/TCH3 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE MC68HC908QB8 MC68HC908QB8 256 BYTES 8192 BYTES USER RAM USER FLASH 10-CHANN
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Functional Description 15.3 Functional Description The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt driven. The following paragraphs describe the operation of the SPI module.
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Serial Peripheral Interface (SPI) Module 15.3.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR, is set. NOTE In a multi-SPI system, configure the SPI modules as master or slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. See 15.8.1 SPI Control Register. Only a master SPI module can initiate transmissions.
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Functional Description controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the frequency of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed. When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its transmit data register.
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Serial Peripheral Interface (SPI) Module SPSCK CYCLE # FOR REFERENCE 1 2 3 4 5 6 7 8 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB SPSCK; CPOL = 0 SPSCK; CPOL =1 MOSI FROM MASTER MISO FROM SLAVE MSB SS; TO SLAVE CAPTURE STROBE Figure 15-4. Transmission Format (CPHA = 0) Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1.
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Functional Description remain low between transmissions. This format may be preferable in systems having only one master and only one slave driving the MISO data line. SPSCK CYCLE # FOR REFERENCE 1 2 3 4 5 6 7 8 MOSI FROM MASTER MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB MISO FROM SLAVE MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 SPSCK; CPOL = 0 SPSCK; CPOL =1 LSB SS; TO SLAVE CAPTURE STROBE Figure 15-6.
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Serial Peripheral Interface (SPI) Module WRITE TO SPDR INITIATION DELAY BUS CLOCK MOSI MSB BIT 5 BIT 6 SPSCK CPHA = 1 SPSCK CPHA = 0 SPSCK CYCLE NUMBER 1 3 2 INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN WRITE TO SPDR BUS CLOCK EARLIEST BUS CLOCK LATEST WRITE TO SPDR EARLIEST BUS CLOCK WRITE TO SPDR EARLIEST BUS CLOCK WRITE TO SPDR EARLIEST SPSCK = BUS CLOCK ÷ 2; 2 POSSIBLE START POINTS SPSCK = BUS CLOCK ÷ 8; 8 POSSIBLE START POINTS LATEST SPSCK = BUS CLOCK ÷ 32; 32 POSSIBLE ST
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Functional Description 15.3.4 Queuing Transmission Data The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the transmit data register only when the SPTE bit is high.
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Serial Peripheral Interface (SPI) Module 15.3.5 Resetting the SPI Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is 0. Whenever SPE is 0, the following occurs: • The SPTE flag is set. • Any transmission currently in progress is aborted. • The shift register is cleared. • The SPI state counter is cleared, making it ready for a new complete transmission. • All the SPI pins revert back to being general-purpose I/O.
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Functional Description In this case, an overflow can be missed easily. Because no more SPRF interrupts can be generated until this OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions can set the SPRF bit. Figure 15-10 illustrates this process.
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Serial Peripheral Interface (SPI) Module 15.3.6.2 Mode Fault Error Setting SPMSTR selects master mode and configures the SPSCK and MOSI pins as outputs and the MISO pin as an input. Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI pins as inputs and the MISO pin as an output. The mode fault bit, MODF, becomes set any time the state of the slave select pin, SS, is inconsistent with the mode selected by SPMSTR.
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Interrupts In a slave SPI (MSTR = 0), MODF generates an SPI receiver/error interrupt request if the ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort the SPI transmission by clearing the SPE bit of the slave. NOTE A high on the SS pin of a slave SPI puts the MISO pin in a high impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission.
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Serial Peripheral Interface (SPI) Module The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to generate a receiver/error interrupt request. The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF bit is enabled by the ERRIE bit to generate receiver/error interrupt requests.
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I/O Signals 15.7 I/O Signals The SPI module can share its pins with the general-purpose I/O pins. See Figure 15-1 for the port pins that are shared. The SPI module has four I/O pins: • MISO — Master input/slave output • MOSI — Master output/slave input • SPSCK — Serial clock • SS — Slave select 15.7.1 MISO (Master In/Slave Out) MISO is one of the two SPI module pins that transmits serial data.
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Serial Peripheral Interface (SPI) Module MISO/MOSI BYTE 1 BYTE 2 BYTE 3 MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 Figure 15-12. CPHA/SS Timing When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can still prevent the state of SS from creating a MODF error. See 15.8.2 SPI Status and Control Register.
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Registers 15.8.1 SPI Control Register The SPI control register: • Enables SPI module interrupt requests • Configures the SPI module as master or slave • Selects serial clock polarity and phase • Configures the SPSCK, MOSI, and MISO pins as open-drain outputs • Enables the SPI module Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE 0 0 1 0 1 0 0 0 R = Reserved Figure 15-13.
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Serial Peripheral Interface (SPI) Module SPTIE— SPI Transmit Interrupt Enable This read/write bit enables interrupt requests generated by the SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register. 1 = SPTE interrupt requests enabled 0 = SPTE interrupt requests disabled 15.8.
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Registers MODF — Mode Fault Bit This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission with MODFEN set. In a master SPI, the MODF flag is set if the SS pin goes low at any time with the MODFEN bit set. Clear MODF by reading the SPI status and control register (SPSCR) with MODF set and then writing to the SPI control register (SPCR).
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Serial Peripheral Interface (SPI) Module 15.8.3 SPI Data Register The SPI data register consists of the read-only receive data register and the write-only transmit data register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register reads data from the receive data register. The transmit data and receive data registers are separate registers that can contain different values. See Figure 15-2.
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Chapter 16 Timer Interface Module (TIM) 16.1 Introduction This section describes the timer interface module (TIM). The TIM module is a 4-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. The TIM module shares its pins with general-purpose input/output (I/O) port pins. See Figure 16-1 for port location of these shared pins. 16.
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Timer Interface Module (TIM) PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 DDRA PTA2/IRQ/KBI2/TCLK PTA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/SCK/AD4 PTB1/MOSI/AD5 PTB2/MISO/AD6 PTB3/SS/AD7 PTB4/RxD/AD8 PTB5/TxD/AD9 PTB6/TCH2 PTB7/TCH3 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE MC68HC908QB8 MC68HC908QB8 256 BYTES 8192 BYTES USER RAM USER FLASH 10-CHANNEL 10-BIT AD
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Functional Description TCLK TCLK (IF AVAILABLE) PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF TCNTH:TCNTL TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 TOV0 ELS0B ELS0A CH0MAX 16-BIT COMPARATOR TCH0H:TCH0L PORT LOGIC TCH0 CH0F 16-BIT LATCH CH0IE MS0A INTERRUPT LOGIC MS0B INTERNAL BUS TOV1 CHANNEL 1 ELS1B ELS1A CH1MAX 16-BIT COMPARATOR TCH1H:TCH1L PORT LOGIC TCH1 CH1F 16-BIT LATCH CH1IE MS1A INTERRUPT LOGIC TOV2 C
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Timer Interface Module (TIM) channel, the TIM can set, clear, or toggle the channel pin. Output compares can be enabled to generate interrupt requests. 16.3.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 16.3.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers.
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Functional Description the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares. 16.3.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal.
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Timer Interface Module (TIM) Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: • When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value.
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Functional Description 16.3.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the counter by setting the TIM stop bit, TSTOP. b. Reset the counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3.
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Timer Interface Module (TIM) 16.4 Interrupts The following TIM sources can generate interrupt requests: • TIM overflow flag (TOF) — The TOF bit is set when the counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow interrupt requests. TOF and TOIE are in the TSC register. • TIM channel flags (CH3F:CH0F) — The CHxF bit is set when an input capture or output compare occurs on channel x.
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I/O Signals 16.7 I/O Signals The TIM module can share its pins with the general-purpose I/O pins. See Figure 16-1 for the port pins that are shared. 16.7.1 TIM Channel I/O Pins (TCH3:TCH0) Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. TCH0 and TCH2 can be configured as buffered output compare or buffered PWM pins. 16.7.
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Timer Interface Module (TIM) effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Writing a 1 to TOF has no effect. 1 = Counter has reached modulo value 0 = Counter has not reached modulo value TOIE — TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP — TIM Stop Bit This read/write bit stops the counter.
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Registers 16.8.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
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Timer Interface Module (TIM) 16.8.
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Registers Writing a 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE — Channel x Interrupt Enable Bit This read/write bit enables TIM interrupt service requests on channel x. 1 = Channel x interrupt requests enabled 0 = Channel x interrupt requests disabled MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TSC0 and TSC2 registers.
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Timer Interface Module (TIM) ELSxB and ELSxA — Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 16-2 shows how ELSxB and ELSxA work.
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Registers In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written. Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset: Indeterminate after reset Figure 16-14.
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Timer Interface Module (TIM) MC68HC908QB8 Data Sheet, Rev.
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Chapter 17 Development Support 17.1 Introduction This section describes the break module, the monitor module (MON), and the monitor mode entry methods. 17.2 Break Module (BRK) The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
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Development Support PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 DDRA PTA2/IRQ/KBI2/TCLK PTA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/SPSCK/AD4 PTB1/MOSI/AD5 PTB2/MISO/AD6 PTB3/SS/AD7 PTB4/RxD/AD8 PTB5/TxD/AD9 PTB6/TCH2 PTB7/TCH3 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE MC68HC908QB8 MC68HC908QB8 256 BYTES 8192 BYTES USER RAM USER FLASH 10-CHANNEL 10-BIT ADC ENHANCE
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Break Module (BRK) ADDRESS BUS[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR ADDRESS BUS[15:0] CONTROL 8-BIT COMPARATOR BKPT (TO SIM) BREAK ADDRESS REGISTER LOW ADDRESS BUS[7:0] Figure 17-2. Break Module Block Diagram The break interrupt timing is: • When a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine.
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Development Support 17.2.2 Break Module Registers These registers control and monitor operation of the break module: • Break status and control register (BRKSCR) • Break address register high (BRKH) • Break address register low (BRKL) • Break status register (BSR) • Break flag control register (BFCR) 17.2.2.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits.
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Break Module (BRK) 17.2.2.3 Break Auxiliary Register The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the MCU is in a state of break interrupt with monitor mode. Read: Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: Bit 0 BDCOP 0 = Unimplemented Figure 17-6. Break Auxiliary Register (BRKAR) BDCOP — Break Disable COP Bit This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit.
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Development Support BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break 17.2.3 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. If enabled, the break module will remain enabled in wait and stop modes.
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Monitor Module (MON) POR RESET NO CONDITIONS FROM Table 17-1 PTA0 = 1, RESET VECTOR BLANK? IRQ = VTST? YES PTA0 = 1, PTA1 = 1, AND PTA4 = 0? NO NO YES YES FORCED MONITOR MODE NORMAL USER MODE NORMAL MONITOR MODE INVALID USER MODE HOST SENDS 8 SECURITY BYTES IS RESET POR? YES NO YES ARE ALL SECURITY BYTES CORRECT? ENABLE FLASH NO DISABLE FLASH MONITOR MODE ENTRY DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED) EXECUTE MONITOR CODE YES DOES RESET OCCUR? NO Figure 17-9.
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Development Support VDD VDD 10 kΩ* VDD RST (PTA3) MAX232 1 1 μF + 3 4 1 μF + VDD 16 C1+ + 1 kΩ 9.1 V 1 μF 10 kΩ + 74HC125 3 2 9 8 PTA4 74HC125 5 6 10 10 kΩ* PTA0 4 VSS 1 5 10 kΩ* IRQ (PTA2) VDD V– 6 7 VDD PTA1 DB9 3 1 μF V+ 2 C2+ OSC1 (PTA5) 1 μF 15 C1– 0.1 μF VTST + 5 C2– 2 9.8304 MHz CLOCK * Value not critical Figure 17-10. Monitor Mode Circuit (External Clock, with High Voltage) VDD N.C. 1 1 μF 3 4 1 μF + C1+ C1– C2+ 5 C2– VDD 16 + 9.
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Monitor Module (MON) VDD N.C. RST (PTA3) VDD 0.1 μF MAX232 1 1 μF + 3 4 1 μF + C1+ C1– C2+ 5 C2– VDD + 3 1 μF 15 + OSC1 (PTA5) IRQ (PTA2) 1 μF VDD V– 6 1 μF 7 10 8 9 10 kΩ 74HC125 5 6 + 74HC125 3 2 PTA1 N.C. PTA4 N.C. 10 kΩ* V+ 2 DB9 2 N.C. 16 PTA0 VSS 4 1 5 * Value not critical Figure 17-12.
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Development Support Table 17-1. Monitor Mode Signal Requirements and Options Mode Serial Mode CommuniSelection RST Reset IRQ cation (PTA2) (PTA3) Vector PTA0 PTA1 PTA4 Communication Speed COP External Bus Clock Frequency Comments Baud Rate VTST VDD X 1 1 0 Disabled 9.8304 MHz 2.4576 MHz 9600 Provide external clock at OSC1. VDD X $FFFF (blank) 1 X X Disabled 9.8304 MHz 2.4576 MHz 9600 Provide external clock at OSC1. VSS X $FFFF (blank) 1 X X Disabled X 3.
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Monitor Module (MON) 17.3.1.2 Forced Monitor Mode If entering monitor mode without high voltage on IRQ, then startup port pin requirements and conditions, (PTA1/PTA4) are not in effect. This is to reduce circuit requirements when performing in-circuit programming. NOTE If the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial power-on reset (POR).
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Development Support 17.3.1.4 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT NEXT START BIT Figure 17-13. Monitor Data Format 17.3.1.5 Break Signal A start bit (logic 0) followed by nine logic 0 bits is a break signal.
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Monitor Module (MON) FROM HOST 4 ADDRESS HIGH READ READ 4 1 ADDRESS HIGH 1 ADDRESS LOW 4 ECHO Notes: 1 = Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times ADDRESS LOW DATA 1 3, 2 4 RETURN 3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte. Figure 17-15.
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Development Support Table 17-4. WRITE (Write Memory) Command Description Operand Data Returned Opcode Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data byte None $49 Command Sequence FROM HOST WRITE WRITE ADDRESS HIGH ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA ECHO Table 17-5.
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Monitor Module (MON) Table 17-7. READSP (Read Stack Pointer) Command Description Operand Data Returned Opcode Reads stack pointer None Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order $0C Command Sequence FROM HOST READSP SP HIGH READSP SP LOW ECHO RETURN Table 17-8.
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Development Support 17.3.2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors.
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Chapter 18 Electrical Specifications 18.1 Introduction This section contains electrical and timing specifications. 18.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 18.5 5-V DC Electrical Characteristics and 18.8 3-V DC Electrical Characteristics for guaranteed operating conditions.
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Electrical Specifications 18.3 Functional Operating Range Characteristic Operating temperature range Operating voltage range Symbol Value Unit Temperature Code TA (TL to TH) – 40 to +125 – 40 to +105 – 40 to +85 °C M V C VDD 2.7 to 5.5 V — 18.
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5-V DC Electrical Characteristics 18.5 5-V DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max VDD –0.4 VDD –1.5 VDD –0.8 — — — — — — — — 50 — — — — — — 0.4 1.5 0.8 Unit Output high voltage ILoad = –2.0 mA, all I/O pins ILoad = –10.0 mA, all I/O pins ILoad = –15.0 mA, PTA0, PTA1, PTA3–PTA5 only VOH Maximum combined IOH (all I/O pins) IOHT Output low voltage ILoad = 1.6 mA, all I/O pins ILoad = 10.0 mA, all I/O pins ILoad = 15.
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Electrical Specifications 18.6 Typical 5-V Output Drive Characteristics 1.6 1.4 VDD-VOH (V) 1.2 1.0 5V PTA 0.8 5V PTB 0.6 0.4 0.2 0.0 0 -5 -10 -15 -20 -25 -30 IOH (mA) Figure 18-1. Typical 5-Volt Output High Voltage versus Output High Current (25°C) 1.6 1.4 1.2 VOL (V) 1.0 5V PTA 0.8 5V PTB 0.6 0.4 0.2 0.0 0 5 10 15 20 25 30 IOL (mA) Figure 18-2. Typical 5-Volt Output Low Voltage versus Output Low Current (25°C) MC68HC908QB8 Data Sheet, Rev.
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5-V Control Timing 18.7 5-V Control Timing Characteristic(1) Symbol Min Max Unit Internal operating frequency fOP (fBUS) — 8 MHz Internal clock period (1/fOP) tcyc 125 — ns tRL 100 — ns tILIH 100 — ns — tcyc RST input pulse width low(2) (2) IRQ interrupt pulse width low (edge-triggered) (2) IRQ interrupt pulse period tILIL (3) Note 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise noted. 2.
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Electrical Specifications 18.8 3-V DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max VDD –0.3 VDD –1.0 VDD –0.8 — — — — — — — — 50 — — — — — — 0.3 1.0 0.8 Unit Output high voltage ILoad = –0.6 mA, all I/O pins ILoad = –4.0 mA, all I/O pins ILoad = –10.0 mA, PTA0, PTA1, PTA3–PTA5 only VOH Maximum combined IOH (all I/O pins) IOHT Output low voltage ILoad = 0.5 mA, all I/O pins ILoad = 6.0 mA, all I/O pins ILoad = 10.
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Typical 3-V Output Drive Characteristics 18.9 Typical 3-V Output Drive Characteristics 1.2 1.0 VDD-VOH (V) 0.8 3V PTA 0.6 3V PTB 0.4 0.2 0.0 0 -5 -10 -15 -20 -25 IOH (mA) Figure 18-4. Typical 3-Volt Output High Voltage versus Output High Current (25°C) 1.2 1.0 0.8 VOL (V) 3V PTA 0.6 3V PTB 0.4 0.2 0.0 0 5 10 15 20 25 IOL (mA) Figure 18-5. Typical 3-Volt Output Low Voltage versus Output Low Current (25°C) MC68HC908QB8 Data Sheet, Rev.
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Electrical Specifications 18.10 3-V Control Timing Characteristic(1) Symbol Min Max Unit Internal operating frequency fOP (fBus) — 4 MHz Internal clock period (1/fOP) tcyc 250 — ns tRL 200 — ns tILIH 200 — ns — tcyc RST input pulse width low(2) (2) IRQ interrupt pulse width low (edge-triggered) (2) IRQ interrupt pulse period tILIL (3) Note 1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2.
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Oscillator Characteristics 18.11 Oscillator Characteristics Characteristic Symbol Min Typ Max — — — 4 8 12.8 — — — Unit (1) Internal oscillator frequency ICFS1:ICFS0 = 00 ICFS1:ICFS0 = 01 ICFS1:ICFS0 = 10 (not allowed if VDD <2.7V) fINTCLK MHz Trim accuracy(2)(3) ΔTRIM_ACC — ± 0.4 — % Deviation from trimmed Internal oscillator(3)(4) 4, 8, 12.8MHz, VDD ± 10%, 0 to 70°C 4, 8, 12.
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Electrical Specifications 12 5V 25 oC RC FREQUENCY,RCCLK f (MHz) 10 8 6 4 2 0 0 10 20 30 40 50 60 Rext (k ohms) Figure 18-7. RC versus Frequency (5 Volts @ 25°C) 12 3V 25 oC RC FREQUENCY,RCCLK f (MHz) 10 8 6 4 2 0 0 10 20 30 40 50 60 Rext (k ohms) Figure 18-8. RC versus Frequency (3 Volts @ 25°C) MC68HC908QB8 Data Sheet, Rev.
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Supply Current Characteristics 18.12 Supply Current Characteristics Voltage Bus Frequency (MHz) Symbol Typ(2) Max Unit Run mode VDD supply current(3) 5.0 3.0 3.2 3.2 RIDD 7.25 3.1 8.5 3.8 mA Wait mode VDD supply current(4) 5.0 3.0 3.2 3.2 WIDD 1.0 0.67 2.0 1.2 mA 0.26 — — 12 125 1.0 2.0 5.0 — — 0.23 — — 2 100 0.8 1.0 4.
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Electrical Specifications 14 13 12 Internal OSC (No A/D, ESCI, SPI) 11 Internal OSC all Modules enabled 10 9 Crystal (No A/D) IDD 8 Crystal All Modules Enabled 7 6 External Reference No A/D 5 External Reference All modules enabled 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 BUS FREQUENCY (MHz) Figure 18-9. Typical 5-Volt Run Current versus Bus Frequency (25•C) 4.5 4 3.5 IDD (mA) 3 Internal OSC (No A/D, ESCI, SPI) Internal OSC all Modules enabled 2.
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ADC10 Characteristics 18.13 ADC10 Characteristics Characteristic Conditions Supply voltage Absolute Supply Current ADLPC = 1 ADLSMP = 1 ADCO = 1 VDD < 3.3 V (3.0 V Typ) Supply current ADLPC = 1 ADLSMP = 0 ADCO = 1 VDD < 3.3 V (3.0 V Typ) Supply current ADLPC = 0 ADLSMP = 1 ADCO = 1 VDD < 3.3 V (3.0 V Typ) Supply current ADLPC = 0 ADLSMP = 0 ADCO = 1 VDD < 3.3 V (3.0 V Typ) VDD < 5.5 V (5.0 V Typ) VDD < 5.5 V (5.0 V Typ) Symbol Min Typ(1) Max Unit VDD 2.7 — 5.
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Electrical Specifications Characteristic Conditions Symbol 10-bit mode Integral non-linearity 10-bit mode Zero-scale error 8-bit mode EZS 10-bit mode Full-scale error 8-bit mode EFS 10-bit mode Quantization error 8-bit mode EQ 10-bit mode Input leakage error 8-bit mode Bandgap voltage Typ(1) Max 0 ±0.5 — 0 ±0.3 — 0 ±0.5 — 0 ±0.3 — 0 ±0.5 — 0 ±0.3 — — — ±0.5 — — ±0.5 0 ±0.2 ±5 INL 8-bit mode (3)(6) Min EIL VBG Unit Comment LSB 0 ±0.1 ±1.2 1.17 1.245 1.
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5.0-Volt SPI Characteristics 18.14 5.
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Electrical Specifications 18.15 3.
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3.0-Volt SPI Characteristics SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT CPOL = 0 NOTE SPSCK OUTPUT CPOL = 1 NOTE 5 4 5 4 6 MISO INPUT MSB IN BITS 6–1 11 MOSI OUTPUT MASTER MSB OUT 7 LSB IN 10 11 BITS 6–1 MASTER LSB OUT Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
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Electrical Specifications SS INPUT 3 1 SPSCK INPUT CPOL = 0 5 4 2 SPSCK INPUT CPOL = 1 5 4 9 8 MISO INPUT SLAVE MSB OUT 6 MOSI OUTPUT BITS 6–1 7 NOTE 11 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defined but normally MSB of character just received a) SPI Slave Timing (CPHA = 0) SS INPUT 1 SPSCK INPUT CPOL = 0 5 4 2 3 SPSCK INPUT CPOL = 1 8 MISO OUTPUT MOSI INPUT 5 4 10 NOTE 9 SLAVE MSB OUT 6 7 BITS 6–1 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defin
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Timer Interface Module Characteristics 18.16 Timer Interface Module Characteristics Characteristic Timer input capture pulse width Symbol Min Max Unit tTH, tTL 2 — tcyc tTLTL Note(2) — tcyc tTCL, tTCH tcyc + 5 — ns (1) Timer input capture period Timer input clock pulse width (1) 1. Values are based on characterization results, not tested in production. 2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
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Electrical Specifications 18.17 Memory Characteristics Symbol Min Typ(1) Max Unit VRDR 1.3 — — V — 1 — — MHz VPGM/ERASE 2.7 — 5.5 V fRead(3) 0 — 8M Hz FLASH page erase time <1 K cycles >1 K cycles tErase 0.9 3.6 1 4 1.1 5.
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Chapter 19 Ordering Information and Mechanical Specifications 19.1 Introduction This section contains order numbers for the MC68HC908QB8, MC68HC908QB4, and MC68HC908QY8. Dimensions are given for: • 16-pin PDIP • 16-pin SOIC • 16-pin thin shrink small outline packages (TSSOP) 19.2 MC Order Numbers Table 19-1.
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Ordering Information and Mechanical Specifications MC68HC908QB8 Data Sheet, Rev.
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How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.