Datasheet

Clock Generator Module (CGM)
MC68HC908GP32 Data Sheet, Rev. 10
66 Freescale Semiconductor
When the tolerance on the bus frequency is tight, choose f
RCLK
to an integer divisor of f
BUSDES
,
and R = 1. If f
RCLK
cannot meet this requirement, use the following equation to solve for R with
practical choices of f
RCLK
, and choose the f
RCLK
that gives the lowest R.
4. Select a VCO frequency multiplier, N.
Reduce N/R to the lowest possible R.
5. If N is < N
max
, use P = 0. If N > N
max
, choose P using this table:
Then recalculate N:
6. Calculate and verify the adequacy of the VCO and bus frequencies f
VCLK
and f
BUS
.
7. Select the VCO’s power-of-two range multiplier E, according to this table:
8. Select a VCO linear range multiplier, L, where f
NOM
= 38.4 kHz
Current N Value P
0
1
2
3
Frequency Range E
0 < f
VCLK
< 9,830,400 0
9,830,400 ≤ f
VCLK
< 19,660,800 1
19,660,800 ≤ f
VCLK
< 39,321,600 2
NOTE: Do not program E to a value of 3.
R round R
MAX
f
VCLKDES
f
RCLK
--------------------------
⎝⎠
⎜⎟
⎛⎞
integer
f
VCLKDES
f
RCLK
--------------------------
⎝⎠
⎜⎟
⎛⎞
–
⎩⎭
⎨⎬
⎧⎫
×=
N round
Rf
VCLKDES
×
f
RCLK
-------------------------------------
⎝⎠
⎜⎟
⎛⎞
=
0 N< N
max
≤
N
max
N< N
max
2×≤
N
max
2× N< N
max
4×≤
N
max
4× N< N
max
8×≤
N round
Rf
VCLKDES
×
f
RCLK
2
P
×
-------------------------------------
⎝⎠
⎜⎟
⎛⎞
=
f
VCLK
2
P
NR⁄×()f
RCLK
×=
f
BUS
f
VCLK
()4⁄=
L round
f
VCLK
2
E
f
NOM
×
--------------------------
⎝⎠
⎜⎟
⎛⎞
=