Datasheet

Clock Generator Module (CGM)
MC68HC908GP32 Data Sheet, Rev. 10
62 Freescale Semiconductor
Figure 5-1. CGM Block Diagram
BCS
PHASE
DETECTOR
LOOP
FILTER
VOLTAGE
CONTROLLED
OSCILLATOR
CLOCK
CGMXCLK
CGMOUT
CGMVDV
CGMVCLK
SIMOSCEN (FROM SIM)
OSCILLATOR (OSC)
PLLIREQ
CGMRDV
PLL ANALOG
÷ 2
CGMRCLK
OSC2
OSC1
SELECT
CIRCUIT
V
DDA
CGMXFC V
SSA
LOCK AUTO ACQ
VPR1–VPR0
PLLIE PLLF
MUL11–MUL0
REFERENCE
DIVIDER
VRS7–VRS0
PRE1–PRE0
OSCSTOPENB
(FROM CONFIG)
(TO: SIM, TIMTB15A, ADC)
PHASE-LOCKED LOOP (PLL)
A
B
S*
*WHEN S = 1,
CGMOUT = B
SIMDIV2
(FROM SIM)
(TO SIM)
(TO SIM)
RDS3–RDS0
R
L
2
E
N
2
P
INTERRUPT
CONTROL
LOCK
DETECTOR
AUTOMATIC
MODE
CONTROL
FREQUENCY
DIVIDER
FREQUENCY
DIVIDER