Datasheet

Analog-to-Digital Converter (ADC)
MC68HC908GP32 Data Sheet, Rev. 10
58 Freescale Semiconductor
4.7.2 ADC Data Register
One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC
conversion completes.
4.7.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal
ADC clock. Table 4-2 shows the available clock configurations. The ADC clock should be set to
approximately 1 MHz.
Address: $003D
Bit 7654321Bit 0
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:
Reset:00000000
= Unimplemented
Figure 4-3. ADC Data Register (ADR)
Address: $003E
Bit 7654321Bit 0
Read:
ADIV2 ADIV1 ADIV0 ADICLK
0000
Write:
Reset:00000000
= Unimplemented
Figure 4-4. ADC Clock Register (ADCLK)
Table 4-2. ADC Clock Divide Ratio
ADIV2 ADIV1 ADIV0 ADC Clock Rate
0 0 0 ADC input clock ÷ 1
0 0 1 ADC input clock ÷ 2
0 1 0 ADC input clock ÷ 4
0 1 1 ADC input clock ÷ 8
1 X X ADC input clock ÷ 16
X = don’t care