Datasheet

Analog-to-Digital Converter (ADC)
MC68HC908GP32 Data Sheet, Rev. 10
56 Freescale Semiconductor
4.6.2 ADC Analog Ground Pin (V
SSAD
)/ADC Voltage Reference Low Pin (V
REFL
)
The ADC analog portion uses V
SSAD
as its ground pin. Connect the V
SSAD
pin to the same voltage
potential as V
SS
.
NOTE
Route V
SSAD
cleanly to avoid any offset errors.
4.6.3 ADC Voltage In (V
ADIN
)
V
ADIN
is the input voltage signal from one of the eight ADC channels to the ADC module.
4.7 I/O Registers
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADCLK)
4.7.1 ADC Status and Control Register
Function of the ADC status and control register (ADSCR) is described here.
COCO — Conversions Complete Bit
In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion.
COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit.
In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It
always reads as a 0.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1)
NOTE
The write function of the COCO bit is reserved. When writing to the ADSCR
register, always have a 0 in the COCO bit position.
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
Address: $003C
Bit 7654321Bit 0
Read: COCO
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write: R
Reset:00011111
R = Reserved
Figure 4-2. ADC Status and Control Register (ADSCR)