Datasheet

Input/Output (I/O) Section
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor 35
$003A
PLL VCO Range Select
Register
(PMRS)
Read:
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Write:
Reset:01000000
$003B
PLL Reference Divider
Select Register
(PMDS)
Read: 0000
RDS3 RDS2 RDS1 RDS0
Write:
Reset:00000001
$003C
Analog-to-Digital Status and
Control Register
(ADSCR)
Read: COCO
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write: R
Reset:00011111
$003D
Analog-to-Digital Data
Register
(ADR)
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:
Reset:00000000
$003E
Analog-to-Digital Clock
Register
(ADCLK)
Read:
ADIV2 ADIV1 ADIV0 ADICLK
0000
Write:
Reset:00000000
$003F Unimplemented
Read:
Write:
Reset:
$FE00
SIM Break Status Register
(SBSR)
Read:
RRRRRR
SBSW
R
Write: Note
Reset: 0
Note: Writing a logic 0 clears SBSW.
$FE01
SIM Reset Status Register
(SRSR)
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
POR: 10000000
$FE02
SIM Upper Byte Address
Register
(SUBAR)
Read:
RRRRRRRR
Write:
Reset:
$FE03
SIM Break Flag Control
Register
(SBFCR)
Read:
BCFE RRRRRRR
Write:
Reset: 0
$FE04
Interrupt Status Register 1
(INT1)
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write: RRRRRRRR
Reset:00000000
$FE05
Interrupt Status Register 2
(INT2)
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
Write: RRRRRRRR
Reset:00000000
$FE06
Interrupt Status Register 3
(INT3)
Read: 000000IF16IF15
Write: RRRRRRRR
Reset:00000000
$FE07 Reserved
Read:
RRRRRRRR
Write:
Reset:00000000
Addr. Register Name Bit 7 654321Bit 0
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 6)